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Efpga ip cores for gf 12lp 12lp rad hard by design IP Listing

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1.8V & 3.3V Radiation Hardened GPIO with Optimized LDO

This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA,8mA, and 16mA, along with a full-speed output enable function. The library ...

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PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+

Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 4.0 operates at 2.5Gbps, 5Gbps, ...

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Efpga ip cores for gf 12lp 12lp rad hard by design IP Listing

1.8V & 3.3V Radiation Hardened GPIO with Optimized LDO

PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+

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