Ethernet 1G TSN MAC core is a full-featured, easy-to-use, synthesizable design that supports various Ethernet TSN standards and supports 10/100/1000M speeds. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 1G TSN MAC IIP is proven in FPGA environment. The host interface of the Ethernet can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
ETHERNET 1G TSN MAC IIP is supported natively in Verilog and VHDL
- Compliant with IEEE 802.3-2018 specification with the below TSN features
- IEEE 802.1Qbu Preemption
- IEEE 802.3br Interspersing Express Traffic
- IEEE 802.1AS Timing and Synchronization
- IEEE 802.1Qbv Enhancements for scheduled traffic
- IEEE 802.1Qav Credits based shaping
- IEEE 802.1CB Frame replication and elimination for reliability
- Supports for Full duplex and Half duplex mode
- Supports upto 10M/100M and 1G
- Supports for GMII/MII/RGMII
- FCS generation supported
- Supports for 802.3.az Energy Efficient Ethernet(EEE)
- Supports VLAN and jumbo frames as an option
- Independent TX and RX Maximum Transmission Unit (MTU)
- TSN features can be enabled/disabled independently
- Cut-through support
- Configurable Transmit and Receive FIFOs
- Supports for MDIO (Clause 22 and Clause 45) Interface
- Supports for Programmable Inter Packed Gap(IPG) and Preamble length
- Comprehensive statistics gathering
- In house UNH compliance tested
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The Ethernet interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
Block Diagram of the Ethernet 1G TSN MAC IP Core