The Floating point Multilier performs single-precision, floating-point multiplication according to the IEEE 754 standard. Each operand and the result is 32-bits wide and consists of 1 sign bit, 8 exponent bits and 23 fraction bits. Results are rounded to the nearest even number.
- IEEE-754 single-precision floating point multiplication.
- Full support for infinities, NaNs and denormals.
- Rounding is to the nearest even number.
- Status flags indicating invalid, overflow, underflow and inexact.
- Optional pipeline registers. Supports one operation per cycle.
- Simple interfacing
- Low gate-count
- High throuhput
- Full source code
- Test harness
- Synthesis scripts for Xilinx, Altera and ASIC
- High performance computing
- Beam forming
- Wireless - MIMO/SDR
- Energy efficiency computing
Block Diagram of the Floating point Multiplier Unit IP Core