The Omnitek HDMI IP consists of the HDMI Rx IP and the HDMI Tx IP. The HDMI Rx IP will convert an HDMI video stream up to 4KP60 to a RGB/YUV video AXI4-Stream with any AUX data in an auxiliary AXI4-Stream. The HDMI Tx IP will convert a RGB/YUV video AXI4-Stream plus AUX data into a HDMI video stream. The HDMI Rx and HDMI Tx IP support HDMI 1.4 and HDMI 2.0 datastreams up to 6.0Gbps.
Digital Content Protection can be provided through the use of external HDCP Rx/Tx blocks.
HDMI channels are de-serialised, checked, synchronized and bonded. The data is decoded to remove the TMDS encoding then unscrambled and de-encrypted by the High Definition Copy Protection IP Core.
The de-encrypted data is de-multiplexed into an RGB/YUV video stream and an auxiliary data stream. The video data stream unpacked, timed, sub-sampled and then mapped as a RGB/YUV AXI4-Stream. The auxiliary data stream is filtered to extract different packets and output as an AXI4-Stream.
RGB/YUV Video data as a AXI4-Stream is mapped, pixel repeated, timed then multiplexed with the AUX Data on a second AXI4-Stream. The RGB or YUV data stream that is produced is then split into separate RGB/YUV streams for output as HDMI
The 3 identical data channels for RGB/YUV scramble the data before encoding as TMDS (Transition Minimized Differential Signalling). The data is then oversampled and buffered before being serialised to provide the HDMI output.
- Very small FPGA resource footprint
- Very low output latency
- Support for image sizes up to 4096 x 2160 at up to 60 fps
- Independent transceiver PHY (GT Core) to allow ease of integration into different designs and packages
- Tx and Rx available as independent IP Subsystems
- Configurable optional cores to minimise resource usage
- Available as reference design
- Fully compatible with other Omnitek IP Cores via AXI4-Stream
- HDMI to SDI conversion up to 4KP60
- SDI to HDMI conversion up to 4KP60
- HDMI to V-by-One conversion
- Display screen interfaces
- Projector interfaces
- Multi-screen display controllers
- Interactive display systems
- HDMI switchers/routers
- HDMI to IP conversion
Block Diagram of the HDMI Subsystem Xilinx FPGA IP IP Core