Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. Optimized for TSMC’s 28- nm high-performance (HP) process technology, the DesignWare® Duet Package of Embedded Memories and Logic Libraries includes standard cells, SRAMs, register files, ROMs, High Performance Kits (HPKs) and Power Optimization Kits (POKs) – all the elements needed to implement a complete SoC. Options for overdrive/low voltage PVTs, high density SRAMs, multi-channel cells, and memory built-in self test (BIST) and repair are also available, enabling designers to achieve the best combination of performance, power and area in their designs. DesignWare Embedded Memories and Logic Libraries are extensively proven in silicon with
billions of units shipping in volume production, lowering project risk and speeding time-to-market.
The DesignWare Memory Compiler and Logic Library IP portfolio for the TSMC 28HPM process provides advanced, built-in power management features that enable system-on-chip (SoC) designers to explore tradeoffs between performance, area and power to generate optimal memory configurations. This dashboard control capability is critical at 28-nm where design and process complexities require sophisticated management of the various tradeoffs to effectively meet stringent end-product requirements and increasingly narrow time-to-market windows. In addition, the integrated STAR Memory System enables highspeed test and repair of embedded memories, delivering higher test quality and yield. The DesignWare Memory Compiler and Logic Library IP solutions have been silicon-proven with billions of units shipping in volume production, enabling designers to lower risk and speed time-to-market.
These high-density embedded SRAMs are optimized to generate memories with the absolute minimum area and power, enabling designers to achieve aggressive critical path requirements. These compilers minimize both static and dynamic power consumption, while the high-speed embedded memory compilers provide a much higher level of performance. The logic libraries include yield optimized standard cells for a wide variety of design applications at 28-nm with multiple threshold process variants and multiple channel lengths.
The DesignWare Logic Libraries offer two separate architectures of 1,200 each to optimize circuits for high density or high speed. The included POKs provide designers with the most advanced power management capabilities.
- Silicon-proven, shipping in billions of chips
- Broad portfolio of high-speed, high density and low-power memory compilers and logic libraries
- Complete standard cell library supporting multiple architectures, VTs, gate biases, PVTs
- Integrated test and repair solution delivers higher test quality and yield, while lowering overall chip areas
- CDL and other industry standard design views