The CS_AD080500S_GF65LPe is an ultra low power, single, 8-bit, 500-MSPS ADC with buffered on-chip Track & Hold, and an interleaved quantizer array for power-efficiency and low bit-error-rate. The ADC can be easily ported to other process nodes and foundries.
- Differential analog and clock inputs with on-chip termination.
- Buffered on-chip Track & Hold.
- Built-in reference and bias circuitry.
- Automatic foreground self-calibration.
- Built-in ESD protection.
- High sample rate
- Ultra low power
- Low bit-error-rate (1E-18)
- High input bandwidth (>1 GHz)
- High-bandwidth communications
- Cable / Set top box
- Test & Measurement
- Radar / Lidar
- Wireless communications
Block Diagram of the Ultra Low Power 8-bit 500-MSPS ADC