The DesignWare XAUI PHY IP is designed for use in any networking or high-end computing SoC solutions. Designed for the latest high-speed backplanes, the XAUI PHY supports the 10 Gigabit Ethernet standards that are commonly used in high-speed communications applications. Based on Synopsys' proven high-speed SerDes technology, the DesignWare XAUI PHY provides a cost effective and extremely low power solution that is designed to meet the needs of today's XAUI designs.
To handle increasing communication system speeds, the XAUI standard is designed to take a 10 Gbps serial stream and divided into four 2.5Gbps serial streams that run over copper traces and chip to chip connections using 8B10B coding at 3.125Gbaud. By taking advantage of copper links, higher performance communications applications can be cost effectively deployed.
The XAUI PHY integrates high-speed mixed-signal custom CMOS circuitry and is compliant with the XAUI base specification. While extremely low in power consumption and area requirements, Synopsys' XAUI PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity.
The DesignWare Ethernet IP solutions consist of configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.
- Extremely low power consumption per lane resulting in significant savings
- Supports IEEE 802.3. Supports popular 130-nm to 28-nm processes
- Excellent performance margin and receiver sensitivity
- On board scope and diagnostics for fast system verification
- GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report
- Simulation model for digital blocks, Behavioral models for analog blocks
- Synopsys’ PrimeTime STA results, Gate-level netlist and SDF timing file
- DesignWare PHY Hard Macro Databook for XAUI. BSDL files for JTAG AC/DC Boundary Scan, ATE test vectors