D&R Slides

An UML-driven Interface Generation Approach for SoC Design with ...	Practical Design and Implementation of a Configurable DDR2 PHY ...	ipPROCESS: A Usage of an IP-core Development Process to Achieve ...
A Twenty-four Processors System on Chip FPGA Design	Embedded Software IP Verification	DDR SDRAM Controller IP Designed for Reuse
A Re-Usable Level 2 cache Architecture	A Cost-Optimized Set-Top Box Architecture	Tailored SoC building using reconfigurable IP blocks
Embedded Software Architecture Specification Developments in ...	Embedded software development using an interpretive instruction ...	SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology
A generalized waveform synthesis mechanism for software radio ...	EDA tools and Design Methodology for multi-FPGA Designing/ Prototyping ...	Finding out the right verification methodology for SOC verification ...

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