32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Multi Protocol PHY
Gabriele Saucier interviews Steve Brown, Director of Marketing, IP Group at Cadence Design Systems
San Francisco, CA, USA
June 9th, 2015
Posted on Thursday Jun. 11, 2015
1:43 Verification with Emerging Memory Models
4:12 An Introduction to Palladium Cloud
2:04 xSPI Standard Explained
3:42 The Storage Combo PHY IP - Nirvana!
2:41 What is Happening at the USB IF Standards Meetings?
4:03 Cloud-Hosted Design Solution - a Full-Service Cloud Offering
2:37 The Reason Why the Vision Q7 DSP Should be in Your Vision and AI SoC
5:47 Passport Partners Program Expands Customer Cloud Deployment Options
4:36 Cadence Cloud - Fast, Painless, Proven Solutions for Cloud-Based Design
7:08