USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
Addressing SoundWire Design Challenges
In this week's Whiteboard Wednesdays video, the second in a two part series, Charles Qi continues his discussion on the Soundwire standard. This week's video focuses on software design challenges and how customers can leverage Cadence Soundwire Design IP to effectively address these challenges.
Posted on Wednesday Sep. 02, 2015
1:43 Verification with Emerging Memory Models
4:12 An Introduction to Palladium Cloud
2:04 xSPI Standard Explained
3:42 The Storage Combo PHY IP - Nirvana!
2:41 What is Happening at the USB IF Standards Meetings?
4:03 Cloud-Hosted Design Solution - a Full-Service Cloud Offering
2:37 The Reason Why the Vision Q7 DSP Should be in Your Vision and AI SoC
5:47 Passport Partners Program Expands Customer Cloud Deployment Options
4:36 Cadence Cloud - Fast, Painless, Proven Solutions for Cloud-Based Design
7:08