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TSMC 4nm (N4P) 1.2V/1.8V Basekit Libraries, multiple metalstacks
Interlaken IP : Ultra Scalable, High Speed, Serial Link-Based Chip-to-Chip Interface
By Devendra Godbole, Engineering Manager IP & SoC Development at Open-Silicon
Posted on Tuesday Apr. 18, 2017
Open-Silicon Channel
IP Subsystems for Deep Learning and Networking Applications
7:46
FlexE IP - A New flexible Ethernet client interface standard
2:24
Optimized ASIC Design Integrating High Speed SerDes
5:45
Smart City Gateway Platform
2:49
IP Solutions Targeted for Ultra High Bandwidth
4:37
Product Standardization: Death to a Growing Market
10:03
Moving Towards Design-Lite for Innovation
05:49
IP Subsystems for Deep Learning and Networking Applications7:46
FlexE IP - A New flexible Ethernet client interface standard2:24
Optimized ASIC Design Integrating High Speed SerDes5:45
Smart City Gateway Platform2:49
IP Solutions Targeted for Ultra High Bandwidth4:37
Product Standardization: Death to a Growing Market 10:03
Moving Towards Design-Lite for Innovation 05:49