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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
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AMBA AHB Verification IP
AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows Module & System level verification. AMBA AHB VIP is a readymade highly configurable SystemVerilog Verification Component suitable for verification of AMBA AHB master and slave DUT. The AHB SV VIP provides all necessary building blocks to easily test master/slave DUT with the AHB protocol. The Verification Component can be easily configured and integrated with the verification environment.
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Block Diagram of the AMBA AHB Verification IP Verification IP
