Local Interconnect Network (LIN) is a single-wire, serial communication protocol based on the UART interface that is gaining popularity as a sub-bus standard in the automotive industry. LIN VIP are reusable components that provide ready made verification environment. Compatible with Local Interconnect Network (LIN) specifications version 1.3 and 2.0. Supports Unconditional, Event-triggered and mandatory Diagnostic frames.
LIN VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Implemented in Unencrypted OpenVera and SystemVerilog.
- Supported RVM, AVM, VMM and non-standard verify env.
- Supports programmable clock frequency of operation.
- Compatible with Local Interconnect Network (LIN) specifications version 2.1
- Supports Unconditional, Event- triggered, Sporadic and Diagnostic frames.
- Simulates LIN cluster with number of nodes the user requires.
- These LIN nodes can be configured as Master, Active Slave or Passive Slave nodes.
- The DUT can either be a LIN 2.1 master or slave device.
- Built-in checkers ensures that LIN Protocol has been followed correctly.
- Supports cluster wake up and go to sleep.
- Supports all types of error insertion and detection
- Checksum error
- Parity error
- Oversize error
- PID start/stop error
- Sync start/stop error
- Break length error
- Delimiter error
- Diagnostic frame errors
- Allows creation of both random and directed testcases.
- Functional coverage for complete LIN 2.1 features.
- Support all types of timing and protocol violation detection.
- Supports callbacks in monitor, slave and master BFMs for user processing of data.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
- LIN Verification IP comes with complete testsuite to test every feature of LIN specification.
- Faster testbench development and more complete verification of LIN designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite containing all the LIN testcases.
- Source code for Master, slave, and monitor
- Examples's showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.