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Compute Express Link (CXL) Verification IP (VIP)
The Cadence® Verification IP (VIP) for Compute Express Link (CXL) is part of the Cadence family of verification IP for PCI Express® (PCIe® ). Built on top of the PCIe 5.0 PHY infrastructure, CXL is an open industry standard for high-bandwidth, low-latency interconnects. It defines the connectivity between the host processor and accelerators/memory devices and smart NICs.
Cadence's VIP for CXL leverages Cadence's mature industry-leading VIP for PCIe. Built on top of an industry-known and -proven platform that was designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system level, the CXL VIP runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce time spent on environment development, and redirect the saved time to cover a larger verification space, accelerate verification closure, and ensure end-product quality.
With a layered architecture and powerful callback mechanism, verification engineers can verify CXL features at each functional layer (PHY, link, transport, and application layer) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space.
Cadence's VIP for CXL leverages Cadence's mature industry-leading VIP for PCIe. Built on top of an industry-known and -proven platform that was designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system level, the CXL VIP runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce time spent on environment development, and redirect the saved time to cover a larger verification space, accelerate verification closure, and ensure end-product quality.
With a layered architecture and powerful callback mechanism, verification engineers can verify CXL features at each functional layer (PHY, link, transport, and application layer) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space.
Features
- Device Configuration
- Host, Device
- Device Type
- Type 1: Caching Devices/Accelerators
- CXL.io
- CXL.cache
- Type 2: Accelerators with Memory
- CXL.io
- CXL.cache
- CXL.mem
- Type 3: Memory Buffers
- CXL.io
- CXL.mem
- Protocol Support
- CXL.io
- CXL.mem
- CXL.cache
- Interface
- Serial
- Link Rate
- Native support: 32 GT/s
- Downgraded support: 16GT/s and 8GT/s
- Link Width
- Native widths (x16, x8,x4)
- Degraded widths (x2, x1)
- FLIT Support
- NULL flit
- CXL.io transaction mapping in FLIT
- CXL.mem/cache protocol FLIT
- CXL.mem/cache control FLIT
- RETRY
- LLCRD
- INIT
- Flex Bus Support
- Alternative Protocol Support
- Framing and packet layout
- Recovery.Idle
- Config.Idle
- Framing error handling
- Arb/MUX
- Weighted round-robin
- Bypass
- Enumeration
- Bypass enumeration
- CXL.io
- Compares read data with expected data based on none/any/many trigger(s) happening for that address
- Configuration space registers
- Memory-mapped registers
- Memory type indication on ATS
- CXL.mem
- M2S Req/RwD
- S2M NDR/DRS
- M2S Req/S2M NDR (cache-related)
- Froward progressing rules
- CXL.cache
- D2H request/response
- H2D request/response
- Cache-ability details and request restriction
- Mem/Cache Link Layer
- Initialization
- Retry flow
- ACK/LLCRD forcing
- Remote Retry State Machine (RRSM)
- Local Retry State Machine (LRSM)
Block Diagram of the Compute Express Link (CXL) Verification IP (VIP)
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