Compute Express Link (CXL) Verification IP (VIP)
Cadence's VIP for CXL leverages Cadence's mature industry-leading VIP for PCIe. Built on top of an industry-known and -proven platform that was designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system level, the CXL VIP runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce time spent on environment development, and redirect the saved time to cover a larger verification space, accelerate verification closure, and ensure end-product quality.
With a layered architecture and powerful callback mechanism, verification engineers can verify CXL features at each functional layer (PHY, link, transport, and application layer) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space.
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Block Diagram of the Compute Express Link (CXL) Verification IP (VIP)
