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DDR3 Memory VIP
DDR-Xactor is a comprehensive memory VIP solution portfolio for DDR4/3, LPDDR3/2, RDIMM/LRDIMM, DFI-PHY used by SoC and memory controller designers using the external SDRAM and DIMM memory components and DFI-PHY developers to ensure comprehensive verification and protocol and timing compliance. DDR-Xactor implements a complete set of models, protocol checkers, and compliance testsuites utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation.
Features
- DDR models support JEDEC DDR3 DRAM (JESD79-3F)
- Flexible and unencypted SystemVerilog timing class models all timing parameters
- Dynamic runtime configuration of memory parameters between DDR4/3/2 (type, vendor, density, speed grades, CL/CWL) and random DQ/DQS timing and jitter
- Comprehensive protocol checks for all DDR3 commands and sequences, data mask and DBI, and detailed timing checks including jitter and write DQS checks
- Optional DDR commands supported for DLL off-mode operations, Input clock frequency change, Extended temperature usage
- Back door block read/write access of sparse memory and MRS registers
- Supports active and monitor model modes
- Extensive callbacks for error injection
- Tracker log monitors improves debug including MRS
- configuration, memory controller source ID mapping, and logical-to-physical address translation, and DDR and DIMM-wide trackers
- Vendors supported: Micron, Samsung, Hynix
Deliverables
- DDR3 BFMs
- User Guide
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