Fully configurable Verification IP that emulates activity bus Master or Slave components, or independent compliance Monitors enables the verification of AXI-based devices.
Unique IP generation capability based on Formal Protocol description enables creation of IP that exactly fits the configuration in use, from simple architectures to full support of tagged out-of-order designs.
IP configurable for all protocol features including bus width, data interleaving depth, tag-width etc.
- Available as ‘Ready-to-use’ transactors, source licenses, tools & services
- Master Transactors generate transactions on command of higher-level testbench
- Slave Transactors recognize and respond to transactions in conjunction with higher-level testbench
- All transactors (Master, Slave & Monitor) detect AXI protocol violations
- supports full range of verification methodologies included directed testing, random and directed random
- Common interface and testcases from System (TLM) to RTL-level supports “Plug & Play” architectural investigation. Choice of of transaction-level interfacing to support all common testbench styles.
- Generated IP available in a variety of simulation languages including SystemC/SCV, Verilog & VHDL to support virtually all simulation environments including all common HDL’s and HVL’s
- Transaction recording in searchable database
- Automatic Protocol-specific Functional Protocol Coverage with support for transactions, expression, non-determinism & transition coverage metrics
- Regular Expression based Formal Protocol definition
- Generated & validated Verificaion IP
- Configuration tools
- Protocol-specific Coverage analysis tools