The Atria Logic High Bandwidth Memory (HBM) Verification IP is a System Verilog (SV) based IP that can be used to verify a HBM memory controller design. The VIP is pre-verified and configurable.
Integrating the VIP in an existing test bench is simple: just configure it and instantiate it as you would instantiate any other design unit. The built-in coverage enables the user to develop test cases to cover all possible input scenarios.
The HBM VIP has been implemented using SV classes. The class descriptions are part of a package that is imported into a top module. The module then instantiates the classes as needed. The module itself needs to be instantiated in the verification environment along with the HBM memory controller design unit that needs to be verified.
- This version of the HBM VIP is compliant with the JEDEC JESD235A specification. The following are the features supported by the VIP:
- Memory size: The HBM VIP supports all the memory configurations mentioned in the JEDEC specification for which the number of banks per channel (for legacy mode) or pseudo-channel (for pseudo-channel mode) is 8 or 16.
- Modes of operation: The HBM VIP supports both legacy mode and pseudo-channel mode of operation.
- Number of channels: The VIP supports between 1 and 8 channels at a time. Each channel will have its own interface and functional coverage.
- Timing checks: The VIP implements timing checks for initialization sequence, low power modes (self-refresh, power down), and other command-command times as detailed in the JEDEC JESD235A specification. Currently, the model supports the SAMSUNG HBM timing parameter values.
- On-the-fly clock frequency change: The JEDEC JESD235A standard allows for the clock frequency to be changed when the HBM is put into one of the two low power modes. The HBM VIP also supports on-the-fly clock frequency change, provided the appropriate protocol is followed. If the frequency is changed when not in a low power mode, the model continues to behave as if the clock frequency has not been changed.
- Protocol analyser: The VIP can be used as a protocol analyser. In this mode, the model will not respond to read/write commands. However, the timing checks will still be in place.
- Coverage: The VIP provides functional coverage details. In addition to implementing coverage by means of SystemVerilog covergroups, the VIP also provides a large number of SVA cover properties that cover the various scenarios that can occur during the course of operation.
- ECC Support: The VIP can support ECC storage, if necessary. The feature is configurable.
- Burst length: The VIP supports burst length of 2 and 4 in legacy mode and burst length of 4 in pseudo-channel mode.
- Mode register configurations: The VIP supports all valid mode register configurations. In case the user configures the mode registers to an invalid setting, the VIP indicates an error.
- Complete SV-UVM test environment for evaluation for limited period of 2 weeks
Block Diagram of the HBM Verification IP Verification IP