The Atria Logic High Bandwidth Memory (HBM) Verification IP is a System Verilog (SV) based IP that can be used to verify a HBM memory controller design. The VIP is pre-verified and configurable.
Integrating the VIP in an existing test bench is simple: just configure it and instantiate it as you would instantiate any other design unit. The built-in coverage enables the user to develop test cases to cover all possible input scenarios.
The HBM VIP has been implemented using SV classes. The class descriptions are part of a package that is imported into a top module. The module then instantiates the classes as needed. The module itself needs to be instantiated in the verification environment along with the HBM memory controller design unit that needs to be verified.