The I2S VIP (I²S Inter-IC Sound, IIS) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting OVM/UVM, this Master and Slave I2S VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The VIP has been interoperability tested with Master and Slave VIP configurations, is silicon proven and comes with a Bus Monitor that performs key protocol checks and reports errors for non compliance with Philips I2S Specification.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
- VIP: I2S Master and Slave
- Compliance: I2S PHILIPS Specification, Cirrus Logic AN282, Wolfson WM8991
- Language: System Verilog
- Methodology: OVM 2.1.1/UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
- Technical Specifications
- Transmitter supports 3 pin configuration
- Supports System Clock and Internal clock
- Right and Left Channel Support
- Supports Transmitter and Receiver
- I2S Master or Slave VIP
- Sample Testbench integrated with proven I2S Master or Slave VIP
- Sample Virtual Sequencer
- VIP User Guide
Block Diagram of the I2S Master and Slave OVM/UVM Verification IP