The PCIE-VR supports all the PCI Express standards, 1.0a, 1.1, and the coming Gen2. All PCIE designs, such as root complex, switches, end points, and bridges, are supported at both Register-Transfer Level (RTL) and Electronic System Level (ESL). To integrate a PCIE design, PCIE-VR uses standard interfaces, such as serial, PIPE, 8/10b, and parallel. A compliance test suite that implements the PCIE compliance checklist from PCI-SIG is also included.
PCIE-VR not only fully model and monitor PCI Express functionality, timing, and protocols but also generates realistic sophisticated concurrent-test scenarios automatically in all the three layers. For the transaction layer verification, PCIE-VR features a multi-threaded traffic generator that greatly simplifies the verification of concurrent access to the designs. For the data link and physical layers, PCIE-VR features powerful randomized state transition loop mechanisms that exhaustively verify the flow control protocol, DLCMSM, and LTSSM.