With today's complex protocols and memory, debug has become one of the most difficult and time-consuming aspects of functional verification. Verdi Protocol Analyzer, available with the VC Verification IP (VIP) portfolio, is a simulator independent, protocol and memory aware debug environment that enables users to quickly debug with any verification environment and easily share simulation results across teams.
Verdi Protocol Analyzer gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. It highlights relationships across the hierarchy, visually unraveling the complex behavior of highly interleaved traffic. Verdi Protocol Analyzer enables engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior. Errors, warnings and messages are annotated to rapidly identify problems in the simulation. It is integrated with Synopsys' Verdi and DVE to easily track behavior between protocol views and signal views.
- Protocol and Memory support including: AMBA®, DDR, Ethernet, HDMI, LPDDR, PCIe and USB
- Side-by-side viewing and scrolling of multiple protocols or interfaces
- Shows all levels of protocol hierarchy
- Sophisticated filtering enables users to focus on objects and behavior of interest
- Simulator independent
- Integrated VIP class reference and user documents
- Integrated log views
- Integrated with signal level debuggers such as DVE and Verdi
- Integrated with Synopsys Verification IPs
- Included in Synopsys VIP Library
Block Diagram of the Protocol and Memory aware Debug Verification IP