English
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
You are here:
Simulation VIP for SAS
The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
View Simulation VIP for SAS full description to...
- see the entire Simulation VIP for SAS datasheet
- get in contact with Simulation VIP for SAS Supplier
Block Diagram of the Simulation VIP for SAS Verification IP
