English
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
You are here:
Synopsys Verification IP for UniPro
Synopsys® VC Verification IP for the MIPI Alliance UniPro protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on UniPro-based designs. VC VIP for UniPro is integrated with Verdi Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand view of protocol traffic. VC VIP for UniPro is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests. VC VIP for UniPro includes support for the MIPI Alliance M-PHY protocol.
View Synopsys Verification IP for UniPro full description to...
- see the entire Synopsys Verification IP for UniPro datasheet
- get in contact with Synopsys Verification IP for UniPro Supplier
Block Diagram of the Synopsys Verification IP for UniPro Verification IP
