Bluetooth 5.1 low energy Baseband Controller, software and profiles
- Verification IP Catalog >
- Memory >
- DRAM >
- DDR
Synthesizable DDR to MIG Bridge
Features
- - Fully synthesizable SystemVerilog/Verilog RTL
- - Up to four independent SRAM ports
- - Any combination of DDR BFM Model type possible
- - Simple sharing schema of physical DDR memory
- - Auto/self-refresh monitoring
- - AXI Interface MIG side of Bridge
- - Targeted for simulation platforms (Cadence Incisive, Synopsys VCS)
- - Targeted for FPGA based systems (Xilinx)
Benefits
- - Expands Memory of any of EasyIC synthesizable DDR BFMs
- - Accommodates up to four DDR BFMs ports in parallel while sharing same physical DDR memory mapped into Xilinx MIG module
- - Enables a 4GB memory size together with all features of the EasyIC BFMs
Deliverables
- Full RTL synthesizable code that can be used by one Customer in any number of projects
- Full documentation of the product
- Full support based on yearly maintenance
View Synthesizable DDR to MIG Bridge full description to...
- see the entire Synthesizable DDR to MIG Bridge datasheet
- get in contact with Synthesizable DDR to MIG Bridge Supplier