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Synthesizable DDR to MIG Bridge
The EasyIC SRAM to Xilinx MIG Bridge is a synthesizable module which facilitates the memory expansion of any of the EasyIC synthesizable DDR BFM models. The Bridge is able to accommodate up to four DDR BFMs ports in parallel while sharing the same physical DDR memory mapped into a Xilinx MIG module. It enables a 4GB memory size together with all the features of the EasyIC BFMs.
Features
- - Fully synthesizable SystemVerilog/Verilog RTL
- - Up to four independent SRAM ports
- - Any combination of DDR BFM Model type possible
- - Simple sharing schema of physical DDR memory
- - Auto/self-refresh monitoring
- - AXI Interface MIG side of Bridge
- - Targeted for simulation platforms (Cadence Incisive, Synopsys VCS)
- - Targeted for FPGA based systems (Xilinx)
Benefits
- - Expands Memory of any of EasyIC synthesizable DDR BFMs
- - Accommodates up to four DDR BFMs ports in parallel while sharing same physical DDR memory mapped into Xilinx MIG module
- - Enables a 4GB memory size together with all features of the EasyIC BFMs
Deliverables
- Full RTL synthesizable code that can be used by one Customer in any number of projects
- Full documentation of the product
- Full support based on yearly maintenance
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