USB 3.0 Verification IP provides an smart way to verify the USB 3.0 component of a SOC or a ASIC. It provides backward compatibility support for earlier versions 1.0 and 2.0 of USB specifications. The SmartDV's USB 3.0 Verification IP is fully compliant with standard USB Specification 3.0. The USB 3.0 VIP can be readily customized and optimized for a wide range of specific system applications.
USB 3.0 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Compliant with USB 3.0 specification version 1.0
- Complete solution for core through chip-level verification
- Supports Superspeed USB 3.0 and 2.0 OTG
- Supports UTMI and PIPE interfaces
- xHCI support
- Comprehensive model support a Host, Device, Hub, PHY
- Configurable PHY Interface width 8, 16 or 32 bits
- Supports dual-simplex, four-wire differential signaling and 8b/10b parallel interface
- PHY interface supports data scrambling to reduce EMI emissions
- Comprehensive compliance testsuite for Protocol, Link, and Physical layer verification
- USB 2.0 core with UTMI/ULPI interfaces
- Operates at Super speed (5 Gbit/s), High(480 Mbit/s) or Full speed(12 Mbit/s) modes
- Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
- Supports Interrupt /Bulk/Isochronous/Control Transfers
- Control transfers supported by Endpoint 0
- Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)
- Separate Endpoint Buffers for IN bound and OUT bound packets
- USB 3.0 low power states support
- Bulk Stream support
- Backward compatible with USB 2.0 and USB 1.0
- Supports constrained randomization of protocol attributes
- Supports all types of error injection and detection
- Supports error injection in all the layers of USB 3.0
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in host and device for various events.
- USB 3.0 Verification IP comes with complete testsuite to test every feature of USB 3.0 specification.
- Rich set of configuration parameters to control the functionality
- Faster testbench development and more complete verification of USB 3.0 designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite containing all the USB 3.0 testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.