Synopsys VC Verification IP (VIP) for ARM® AMBA® AXI™ provides complete protocol support for AXI3™, AXI4™, AXI4-Lite™, AXI4-Stream™, ACE™, ACE-Lite™ , AHB™ and APB™ interfaces. With a comprehensive set of protocol, methodology, verification and productivity features, users are able to achieve rapid verification convergence on their AMBA-based designs.
- Complete protocol support for AXI3, AXI4, AXI4-Lite, AXI4-Stream, ACE, ACE-Lite, AHB and APB
- Configurable interconnect model for AXI, ACE and AHB
- Port level protocol checks for all interfaces
- System-level checks for protocol, data integrity and cache coherence
- Backdoor access to ACE master cache
- Debug port for transaction tracking on waveforms
- Ability to control delays for valid and ready signals with respect to reference events
- Ability to control signal values during idle periods
- Testbench development is accelerated with the assistance of built-in verification plans, example tests and sequence library.
- Built-in coverage points integrate with the verification plans showing progress towards achieving coverage goal.
Block Diagram of the VC Verification IP for AMBA 4 AXI
Video Demo of the VC Verification IP for AMBA 4 AXI