eFPGA IP Core
: Embedded FPGA
eFPGA stands for embedded Field Programmable Grid Arrays. An eFPGA is an FPGA core that is obtained or acquired as an IP which can be licensed and placed inside an ASIC. This allows designer add some flexibility to their ASIC, by changing its functionality after tapeout.
ASIC designs are fixed by nature, making them rigid and unchanging, a misfit if you are looking for a modifiable solution whose configuration can be changed in the field as needed. This is what has ultimately led to the utter popularity of eFPGA IP Cores.
A typical embedded FPGA (eFPGA) IP block comprises of a multitude of logic cells that are programmable even after the ASIC is deployed in the field. It also contains a fabric which essentially serves to interconnect the various components together to create the desired functionality.
An eFPGA or embedded FPGA allows embedding an FPGA IP core into the ASIC/SoC directly. This eliminates the need for any external FPGA chips and thereby saves: power, space and price. An ASIC comprising of an eFPGA is extremely easy to modify and upgrade without having to redesign or remanufacture the component. This also opens up the possibility for adding features, enabling the designer add functions and introduce variability in their product.
One advantage of an eFPGA is the fact that the FPGA IP core can be easily modified and customized without having to remanufactured new chips or changing the design of the SoC. another advantage is that as compared to a system comprising or discrete or individual FPGAs, a system with an eFPGA tends to run on lower power. A greater degree and opportunity for customizability allows designers to ship ASIC products earlier to the market even in an uncertain market requirement because they can always update the eFPGA functionality later on.
When implementing an embedded FPGA, you can choose between using either a soft IP or a hard IP. Most people would recommend using hard IP with an eFPGA considering it eliminates the need for creating a tangible, custom design for validation. A hard IP core can be used as a tile or array or even on its own to build a larger FPGA array. As such, you no longer need additional testing to ensure that the design works when physically implemented.
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