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Open Verification Methodology: Why Now?
April 01, 2008 -- edadesignline.com Cadence and Mentor Graphics recently announced and shipped the Open Verification Methodology (OVM). This initiative focuses on providing a single, open, and interoperable SystemVerilog-based methodology and supporting class library. But why introduce a new methodology now? With at least three other SystemVerilog methodologies already available, why add another to the mix? The simple answer is that goal of the OVM is to reduce the number of methodologies available, thereby improving the productivity of SystemVerilog users, including designers, verification engineers, VIP providers, and even EDA vendors. In order to achieve this, OVM must be completely open, enable full interoperability, provide advanced functionality, and offer a long-term growth path. The SystemVerilog Language Race is Over When SystemVerilog was standardized over four years ago, users liked the idea of a single language with constructs to handle not just design, but verification as well. As simulation vendors started implementing these features, customers started using them and asking for others. This trend continued for several years, as customers pushed vendors to support the language constructs they needed. But what happened along the way was a shift from needing language constructs to a requirement to build a reusable verification environment. Customers realized that the important factor was how they built the environment, not which language constructs were involved. Fast forward to today when we see that most of the testbench language constructs have been implemented in simulation tools. In order to deliver on the original promise of SystemVerilog, what is needed is the ability to create modular verification environments that can use verification IP (VIP) components that have been created somewhere else - either on another project within the company or by an external source such as a partner or a VIP supplier.
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