Borrowing from software to use SystemVerilog test bench debug & analysis
By Bindesh Patel and Amanda Hsiao, SpringSoft USAEmbedded.com (10/23/08, 09:00:00 AM EDT)
Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many of today's applications take advantage of this trend. An important point that is often missed is the accompanying growth in verification complexity.
Indeed, the verification task for a design that is twice as big is actually more than doubled. The verification team has to deal with a bigger statespace and the application, which is what the verification environment attempts to mimic, gets much "bigger".
Simply building faster tools like simulators will not solve this problem. Rather, it requires capabilities and associated methodologies that make it easier to set up complex verification environments - environments that in the end ensure that the application on the chip works as expected.
Fortunately, SystemVerilog provides a compelling advantage in addressing the complexity challenge. It is not simply a new language for describing complex structures, but a platform for enabling advanced methodologies and automation.
Each of the three key aspects of SystemVerilog has a significant role. The synthesizable design constructs that have been added to SystemVerilog make it possible for designers to code at a higher level of abstraction, often mapping more accurately to the function they are designing and the way they think about it.
The new assertions capability allows users to very concisely describe a behavior that needs to be checked. But it is the verification aspect that provides the biggest bang for the buck, as evidenced by its rapid adoption.
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