Managing Complex SoC verification using plan based verification techniques
By Freescale Semiconductor Inc. and STMicroelectronics NV
Meeting the quality requirements of a complex SoC requires managing large verification projects. In this article, we recount a recent experience with a verification management solution (Incisive Enterprise Manager) from Cadence, for the verification of a 32-bit microcontroller project for the automotive industry.Project overview
Our project involved a dual core, 32-bit microcontroller for the automotive safety market. The device was designed as part of the Joint Development Program (JDP) between Freescale and STMicroelectronics.
The verification project was split between the two companies working together across five sites on two continents. Project managers were challenged to meet the high quality requirements of the automotive safety industry, so we needed to organize the verification teams to achieve maximum efficiency.
Our documentation needs would be highly demanding as we worked toward certification for the safety standard IEC 61508. On previous projects, we found the design documentation provided a starting point for our verification engineers to extract the design features and write a verification plan. However, this was far from efficient because the approach offered no clear linkage and the process was entirely manual.
Also on previous projects, we used a process where all tests were implemented and added to the regression list so they could be rerun with each new revision of the design database. The goal was clear: get all the tests to pass. However, there was no direct form of feedback to substantiate whether or not the verification plan was fulfilled. While we wanted better linkage between the regression results, verification plan, and the design documents, we lacked the ability to automate this process. In order for us to get a framework for the verification work across the various work groups, our flow had to be manually pre-planned and documented.
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