55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
FPGA compilation on-site or in the cloud
Rick Kuhlman, National Instruments
EETimes (8/9/2010 7:10 AM EDT)
It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements. Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.
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