The continuing march of VLSI technology toward ever-smaller feature sizes has reduced previous single-chip designs to the scale of circuit components. It is therefore tempting to leverage the considerable design efforts that went into, say, an advanced RISC microprocessor by simply dropping the entire circuit into a larger design.
The simple analogy that comes to mind is the printed-circuit board, where previously designed and tested ICs are soldered onto a board containing interface circuits that link to a bus. However, the analogy really doesn't help a designer faced with building an 0.18-micron design rule IC. Printed-circuit-based design seems easy only because the problems it poses have been worked out over decades, during a time of less rapid change.
If the same method is going to work for large-scale IC design, the industry will have to conjure an infrastructure and tool suite that will guarantee predictable results. Of cour se, the customers for those tools would like to have them right now. Thus, the scramble is on to discover the ideal mix of technologies that will make the concept fly.
|Jacob Greidinger of Aristo Technology and Rami Friedlander of GigaPixel have joined forces to create a design method for the smooth integration of complex cores. |
With this week's Focus section covering intellectual-property (IP) reuse, EE Times is initiating an in-depth look at the projects that are getting results, along with analysis from industry experts on what is working and what isn't. The diversity of the strategies being developed mirrors the diversity of the electronics industry itself. System design at the chip level has become much more than simply linking a digital proc essor with memory subsystems. In a real sense, the electronics industry is going through a radical shrink from larger-scale packaging systems to single-chip solutions.
That process is being accelerated by current market trends that demand small, portable systems with a variety of signal processing, wireless and real-time media stream capabilities. Single-chip designs offer many advantages in realizing these new goals, but the problem of mixing and matching digital, mixed-signal and memory-circuit types on a single chip is unexplored territory.
Consider the experience of GigaPixel Corp. (Santa Clara, Calif.), which has created a 3-D graphics processor core for the reuse market. Designing the complex processor was only the beginning. The smooth integration of such a major circuit block in an even larger circuit proved to be a thorny problem. And, without a quick and easy integration path, GigaPixel's business model of selling cores would not work.
As Rami Friedlander, GigaPixel's vic e president of engineering, and Jacob Greidinger, executive vice president and CTO of Aristo Technology Inc. (Cupertino, Calif.), explain in their article, "A company gets significant revenues only when customers' chips roll out, providing a strong incentive to make sure customers can integrate the IP as quickly as possible." A combination of configurable peripheral functions along with a design tool from Aristo called IC Wizard has produced a methodology for creating reusable IP that meets the company's requirements.
As a result, the 3-D graphics cores can be adapted and scaled from workstation-level applications down to handheld wireless products. In addition to the design tool, heavy customer support and the flexibility of configurable circuit elements were essential in getting an efficient design flow.
However, as Craig Lytle, vice president of the IP business unit at Altera Corp. (San Jose, Calif.), points out in his piece, eliminating consulting services will be essential for the grow th of a reusable-IP industry. "IP can only deliver on the promise of better products faster if it can be used-and reused-easily," Lytle said. "Yet many IP providers continue to include a high degree of consulting in their business models, which inhibits the scalability that is necessary for the broad adoption of IP." Altera is promoting a consultant-free approach with its MegaWizard plug-in, which allows designers to create fully "productized" designs targeted at programmable logic arrays.
Taking a diametrically opposite approach, some companies focus on the mask level. Once a circuit design has made it to the tapeout stage, many of the performance, verification and test issues have been resolved. This represents a sizable investment in itself, and it makes sense to try and preserve this work when the design is slated for reuse. Called "hard IP," mask-defined circuits offer an opportunity for a more realistic "drop-in" design strategy. Highly structured circuits such as memory blocks may represent t he greatest opportunity for hard IP, since their basic role in a system remains the same
as designs evolve. As Mark-Eric Jones, vice president of intellectual property at MoSys Inc. (Sunnyvale, Calif.), explains, "for significant reuse, IP must cross many process generations." MoSys has created a shrinkable static-RAM memory design that can span process generations and is available in a mask-level configuration.
Apart from these specific strategies, which spring from the established technology of design houses, other companies are looking at the larger issues of design flow and IP library creation and maintenance.
For example, Synchronicity Inc. (Marlboro, Mass.) is looking at the big picture of design flow, tool and library integration. "A new model is emerging in which the design team acts as the system integrator, while outsourcing such roles as library development [and] incorporation of semiconductor intellectual-property cores," said Mark Miller, Synchronicity's vice president of marketing and business development. The company proposes a "virtual project team" concept as a route to fully address the complexities of reusable IP.