Trent McConaghy - Solido Design Automation
EETimes (11/5/2012 10:33 AM EST)
In TSMC 28nm process and as process nodes scale, achieving target yields can be extremely challenging. Nowhere is this truer than for memory circuits, which aggressively adopt next bleeding-edge process nodes to help meet increasingly tighter performance specifications and higher levels of integration.
This article reviews the challenges raised by process variation, and in particular for memory with its high-sigma components. It then discusses an approach to address variation with accurate statistical MOS modeling, plus the ability to analyze billions of Monte Carlo samples in minutes. This solution is now in place and rapidly gaining adoption.
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