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Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
The Third Decade: The FPGA as SoC
Ron Wilson, Altera Corporation
In 2003, amidst the recessionary hangover from the dot-com crash, Altera began its third decade. It was a year of endings: the tragic loss of the space shuttle Columbia, the last contact with the spacecraft Pioneer 10, the last VW Beetle from the assembly line. And it was a year of beginnings: the Iraq War, the start of the great bull market in U.S. stocks, the first trans-sonic flight of the privately-developed SpaceShipOne, the first manned spaceflight by China.
In the world of system design, the elements had quietly aligned for the next stage in the evolution of FPGAs. Use of the most aggressive CMOS technology had given FPGAs the logic density and speed to implement a CPU core and its peripherals in a single chip. Altera had released Nios, a RISC CPU core optimized for FPGAs, and partners had developed FPGA implementations of other popular CPU cores as well. Avalon, a multi-master bus architecture tuned for use in programmable logic, normalized interconnects between CPUs and subsystems on the chip. And a tool to add automation to the process of assembling intellectual property (IP) into an FPGA-based SoC, SoPC Builder, reached the market.
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