MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
Lowering Barriers to Entry for ASICs
By TIRIAS Research
There has never been a better time to build your own custom application specific integrated circuit (ASIC). Despite the talk of Moore’s Law slowing and the cost of new chips rising, there are many opportunities to turn your sensor-driver design or your multi-chip controller into a small ASIC to lower costs and protect your intellectual property (IP).
This paper will explore the different ways in which companies are building chips that reduce cost, space, power, while adding features, and protecting the designer’s IP.
If you wish to download a copy of this white paper, click here
|
Arm Ltd Hot IP
Related Articles
- ASICs Bring Back Control to Supply Chains
- Consider ASICs for implementing functional safety in battery-powered home appliances
- Implementing floating-point algorithms in FPGAs or ASICs
- Asynchronous reset synchronization and distribution - ASICs and FPGAs
- Custom ASICs for Internet of Industrial Things (IoIT)
New Articles
- Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)
- SoC NoCs: Homegrown or Commercial Off-the-Shelf?
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
- Embracing a More Secure Era with TLS 1.3
Most Popular
E-mail This Article | Printer-Friendly Page |