Watch out for compatiblity, complexity issues for future embedded Flash

The demand for performance and functionality is ever increasing and a key component of that is rewrite-ability of both code and data. Larger operating and application codes, as well as configuration and personalization codes, are stored on various IC components, requiring field upgrade capability.

Moreover, various types of data require nonvolatility. With systems becoming increasing portable and smaller in size, various conventional rotating magnetic media is designed out and silicon programmable elements are being substituted. These trends present significant opportunities for flash and embedded flash. The question is whether embedded flash is ready to serve these demands and keep up with the pr ojected increasing demands well into the future.

Beyond the traditional decision factors of functionality, performance, cost, size, power consumption and reliability, the vision of integrating flash memories into a complex multi-function design on a system-on-chip (SoC), is driven by access to a logic-compatible, reusable embedded flash technology intellectual property (IP) and its widespread availability from multiple sources.

With wafer fab construction costs starting at a $1-2 billion and technology upkeep requiring hundreds of millions of dollars in ongoing capital equipment investment, most companies find the costs prohibitive to participate. For these reasons, multiple fab process technology sources are very desirable. Having a design that is transportable from fab to fab is especially important if the design makes use of significant IP blocks. Because of this, the nonvolatile memory (NVM) technology that is widely available from multiple wafer foundries and offers circuit designers th e required flexibility will naturally emerge as the standard.

Indeed, reusable and available IP is key for fab portability. To that point, there is a flurry of activities in firms joining forces for product development, IP sharing and licensing arrangements, resulting in the development and proliferation of new products, new IP and new standards.

Logic dictates

More important, the success of a designer's "multiple fab portability" strategy will depend on the degree of compatibility of the NVM with the logic process and the degree of complexity the NVM process might add to a specific fab. In addition, with NVM quickly becoming the paradigm in a plethora of memory-centric IP blocks, the technology roadmap will increasingly be dictated by the logic process development roadmap, instead of the NVM roadmap. Finally, once compatibility is established, it is also important to evaluate yield and robustness of the design.

In general, with typical flash memory pr ocessing, complexity is added from the introduction of the floating gate for charge storage and retention, high-voltage transistors, as well as designs for routing the required high voltages to the memory array; and the complexity of decoding, sensing, timing circuits, and algorithms stored in state machines.

In the deep sub-micron era (0.18 micron and smaller), tooling cost is a substantial part of the total manufacturing cost independent of production volume. The silicon, packaging and test costs represent a portion of the total cost that is dependent upon the production volume. With increasing tooling costs, reconfigurable ICs, which can generate application-specific products with simple modification of the codes, represent an attractive value proposition. The yield, ease of use and debug for reprogrammable NVM becomes paramount as any nonconforming IC magnifies the cost of production.

In essence, for complex logic processes, reprogrammability becomes the compelling reasons for integrat ion amongst factors such as performance enhancement, added features, footprint reduction and power saving. As the overhead cost of the flash is reduced, the crossover point shifts in favor of SoC integration. The process overhead cost combined with the silicon utilization (design overhead cost) determines the crossover point for a given embedded flash technology. Thus, designers need to evaluate the flash architecture and the impact its implementation has on the targeted logic process.

A by-product of that integration will be the impact on the yield. Yield is an aggregate function of both the flash and other integrating components. Obviously, the more flawless the flash, the higher the yield. High yield is achieved by low added process overhead, simple designs with low overhead, robust testability and reliability, high efficiency of silicon utilization, and the ability to quickly and effectively solve problems. In stacked-gate reprogrammable NVM, for example, the thin tunneling (or floating gate) oxi de is more prone to yield loss during manufacturing and reliability yield failures postproduction, due to the increasing difficulty in manufacturing defect-free thinner oxides.

Traditionally, more intelligence had to be designed for error correction circuitry, state machines for algorithmic operations, and similar techniques to mitigate the yield and reliability issues. There are obvious disadvantages with these techniques such as larger silicon area of each device subject to yield loss, more circuits to debug, longer test times and more power consumption. Thus, designers need to fully evaluate the yield component of the logic process. Indeed, the design might be portable from fab to fab, but yields vary, limiting the designer's choice in fab partners.

A non-traditional cell design such as SST's NVM cell is designed to be logic compatible. For example, the split-gate (SuperFlash) cell design lends to a flexible architecture requiring a few simple peripheral circuits to support the memory ope rations; no state machine or algorithmic operation is required.

Fundamentally, the technology is based on thick oxides for charge transfer, which assures future scaling capability. The coupling (floating) gate oxide is never subject to a high electric field stress (strong coupling to high-voltage node); thus, remains reliable during the life of the device. The SoC development cycle time and cost is reduced because the simpler design results in easier debug effort, reduced test and faster yield time.