More functions require balanced SoC design
More functions require balanced SoC design
By Mike Hundt and Rich Evans, EE Times
May 23, 2003 (9:54 a.m. EST)
Two interesting applications for systems-on-chip are set-top boxes and hard drives. Those apps are good fits for SoC devices in that they have the potential for high volumes and good value and are well-defined "systems." Both applications have strong cost constraints.
A set-top IC combines a number of functions that are common to most set-top boxes. They include the microprocessor unit; one or more memory interfaces; an MPEG decoder; a graphics and display unit; an encoder for various video formats, such as PAL, NTSC and Secam; an audio subsystem with digital signal processor for various audio formats; and such peripherals as parallel I/P, a smart-card interface and an infrared transmitter. Other functions may be needed, depending upon the customer and the SoC specifics.
A hard-drive IC can contain virtually all of the electronics of a modern drive. The addition of a preamp, some memory and a power device completes the system. Functions in the SoC can include read-channel circuitry, DSP, memory for data buffering, error correction, bus interfaces, and servo and motor control.
In the past, you may have handled these various functions using separate, individually packaged components interconnected on the printed-circuit board. With the development of the SoC, integration and compatibility issues that previously were managed in the board design now must be handled in the IC and package design. Two examples of these new challenges are designing the power distribution to control switching noise and protecting analog circuits from noise generated by the switching activity of a digital bus. The PC boards are smaller, simpler and cheaper, but these advantages come at the expense of a more difficult design and increased complexity in the package and the IC.
The design problem extends to three levels of the final product: the IC, the IC package and the system pc board. Optimizing the design at all three le vels requires balancing the capabilities of each level. You can achieve this optimization by working closely with all of the designers. While there are various requirements at each level, the goal is to minimize complexity and cost and to assure performance.
The application board may have constraints set by cost, marketing, the application environment, physical size limitations and power requirements. You can generally handle these concerns by keeping the board as simple as possible. Board complexity is strongly affected by the pin density, the relative locations of the signal and power/ground pins, and the order of signals. The board also imposes electrical performance requirements, which demand attention to the design of any high-speed signals. You must control electromagnetic interference and must provide adequate power/ground distribution to all parts.
The IC may contain functional blocks that you obtain from different sources, analog and digital sections, many clock domains, many interfa ces, multiple supply voltages and embedded memory. The floor plan of the chip and the placement of the I/Os are major considerations. Power/ground pad placement and distribution are subject to various rules and can strongly affect the IC's performance. Many SoC devices require several supply voltages, complicating the design.
Also, the package is between the board and IC, and must satisfy requirements set by both. You must select and design the package to allow efficient assembly in high-volume production, minimize cost, provide adequate electrical performance and dissipate the heat generated by the IC. Because the SoC is the only major IC on the board, its footprint and requirements can take precedence over other components.
From an engineering perspective, it's most interesting where the levels interact, and this is where you can perform optimizations. The package and IC interact where the connections are made at the I/O pads. The I/O pad locations and the signal, power and ground assignmen ts will define much of the package's design. The capabilities of the package technology, in turn, can dictate feature placement, for instance in defining the pad pitch. Usually the package must dissipate the heat generated by the IC. It must supply adequate power; that is, it must have low impedance through its power distribution system. The locations and number of the power and ground pads on the IC will affect the power distribution characteristics of the package.
There is a similar situation at the interface between the package and the pc board. The package footprint and pinout determine the complexity of the board in terms of feature size and routability. The capabilities of the board technology will define your options for package size and footprint. Signal location and order on the package pins determine the complexity of the routing and strongly affect the electrical performance. In general, simple routing is easier to control and has better electrical characteristics. The power distribution s cheme on the board may limit what you can do on the package.
In the past, the IC design would dictate the requirements for the package and the system. But the end result of the interactions discussed is that the usual pecking order is now reversed: Limitations and requirements set at the board level now feed back through the package to the IC, where they can define a significant portion of the IC's design. Those who fail to see and accept this reversal do so at their peril.
Co-design is an effective way to handle the multiple, often-conflicting, requirements that exist.
To satisfy the constraints, a number of design variables are available. They include package style and construction, routing and layer usage, IC pad location, IC pinout, package ball pitch and pattern, and package pinout. Do not treat each of these variables independently because each affects the choices available in the others. The effects of the variables are often different at each interconnect level.
Mike H undt is director of package development and Rich Evans is senior staff engineer at ST Americas (Carrollton, Texas). They can be reached at firstname.lastname@example.org and email@example.com.
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