Complex System-on-Chip (SoC) designs are fast becoming commonplace in today’s applications. Hardware designers must overcome many complex and challenging issues regarding cost, time-to-market (TTM), performance, power, capacity, quality and IP integration. The platform used to implement the SoC design, greatly impacts all of these issues and is a fundamental decision the hardware designer must make at the start of each new project. Due to the complexity and performance inherent in most SoC applications, designers, historically, were limited to cell-based ASIC technology. Cell-based ASIC technology offers the performance, power and capacity needed for modern SoC applications. However, the technical advancements in shrinking geometries have driven reticle cost through the roof. This exponential increase in reticle cost translates to excessive Non-Recurring Engineering (NRE) cost, making cell-based ASIC platforms too expensive for all but the highest volume applications (quarter million plus units per year).
New FPGA technologies, with greater capacity, performance and embedded IP, offer SoC designers another viable hardware platform for today’s applications. The programmability of the FPGA allows fast time-to-market, which is extremely critical to the success of a new product. However, the staggering per-unit cost of high-end FPGAs is prohibitive for all but the lowest volume applications (few thousand units per year).
The two extremes of cell-based NRE and FPGA per-unit cost have left a significant void in the market. This void has lead to a market demand for a cost-effect solution suitable for applications ranging from 5k to 1M units per year. In the past year that market demand has led to the emergence of a new, innovative, product called the Structured ASIC. Structured ASIC technology overcomes the two extremes by offering SoC designers a solution with the capacity and performance required for modern SoC applications but without the exorbitant NRE of the cell-based ASIC and exorbitant per-unit cost of FGPA technology.
Initially, this paper will provide a technical and market overview of the Structured ASIC. This will be followed by an analysis of the key issues associated with SoC design: cost, time-to-market (TTM), performance, power, quality and IP integration. Finally, all of these issues and how they relate to a Structured ASIC implementation are compared and contrasted to the other platforms available. After reading this paper, the hardware designer will have enough understanding of Structured ASIC technology and how it relates to the alternative implementations to make an informed decision on which platform to use for future SoC applications.
1. OVERVIEW OF THE STRUCTURED ASIC
As mentioned in the introduction, Structured ASIC technology emerged to bridge the gap between cell-based ASIC and FPGA solutions. For one to understand how Structured ASIC technology makes this possible, one must first understand the technology. This section will provide an overview of the Structured ASIC technology and the market it serves.
A Structured ASIC is different from a traditional gate-array due to its, well, structured nature. Gate arrays contain a ‘sea-of-gates’ across the entire die. This ‘sea-of-gates’ is basically an array of uncommitted transistors. While Structured ASICs offer an array of partially or completely formed macro blocks. These macro blocks are fully optimized in terms of size and performance. They are similar to the FPGA logic cells but do not contain the additional overhead required for field programmability. So instead of the traditional ‘sea-of-gates’, Structured ASICs contain more of a ‘sea-of-macros’. New methodologies and tool flows have been adopted to optimize utilization of these macros. This ‘sea-of-macros’ approach increases performance and capacity to the point where the Structured ASIC is a very viable solution for today’s demanding SoC applications.
Reducing TTM is one of the most important factors driving the Structured ASIC industry. TTM is optimized by reducing the design cycle and by reducing the manufacturing cycle. Providing pre-designed, built-in features and functions minimize the design cycle. Functions such as configurable IO, power and ground grids, block RAM, timing generators and other embedded IP. Since there are fewer layers that need to be processed the manufacturing cycle for a Structured ASIC is considerable shorter than the manufacturing cycle required for a cell-based ASIC.
Embedded within the ‘sea-of-macros’, Structured ASICs contain the timing and performance critical IP needed for complex SoC designs. Structured ASIC products, that are currently available, contain embedded IP blocks such as DLL, PLL, DDR and a wide variety of configurable IO. Structured ASIC vendors also support most of the functional IP required such as processors, peripherals and communication cores. However, most vendors prefer to support soft, synthesizable, IP, whenever possible, to maintain enough flexibility, to support a majority of their customers. IP Integration will be covered in detail later in this paper.
In addition to functional IP, Structured ASIC products also contain large amounts of high-performance, initializable SRAM. Both single port and dual port SRAM is available in the quantities needed for embedded processor applications. SRAM can be implemented using either distributed memories or block RAM. Each design approach has its advantages and disadvantages. Distributed memory is implemented using the logic already available in the ‘sea-of-macros’, making it extremely flexible but of lower performance. Block RAM is implemented using hard embedded IP blocks that are predefined in terms of size and performance but are usually word and word size configurable. The block RAMs offer high capacity and performance but are not suitable for applications that require many different small sized memories at various places on the die. Leading Structured ASIC vendors support both types of memories within their products.
Figure 1, shown below, illustrates the architecture of a Structured ASIC.
A hybrid development process is utilized by some of the Structured ASIC providers, such as AMI Semiconductor, that produces an additional cost and TTM savings over Structured ASICs that are developed in a single process. AMI Semiconductor’s Structured ASIC product line, XPressArrayTM, is developed utilizing two different technologies. A high-performance Deep Sub-Micron (DSM) technology, TSMC 0.18um, is used for the base architecture. While a more mature technology, such as 0.35um or 0.25um, is utilized for the top-level metal routing. The base structures are stockroomed until needed, with all of the customization being done in the upper metal layers. By using this development process the extra cost of purchasing DSM reticles for each new design is avoided, significantly lowering NRE cost. Structured ASIC products that are developed using a single process technology must purchase DSM reticles for each new design.
Some companies that offer hybrid Structured ASIC products, such as AMI Semiconductor, use their own fabs to process the upper metal layers for each customer application. The custom device can be developed while optimizing both cost and schedule. This characteristic of Structured ASICs is extremely critical to meet the decreasing TTM demands on today’s applications. AMI Semiconductor’s XPressArray can go from T0 to prototype in less than 14 days. This quick-turn capability not only supports the critical TTM of single applications but can also be used to support entire product lines by quickly and cost-effectively producing product derivatives.
Figure 2, illustrates the metal utilization of a Structured ASIC. The base architecture, up through M2, contains the ‘sea-of-macros’, and at least a portion of the embedded IP, which are both comprised of high-performance DSM transistors. Some types of embedded IP will utilize layers in the base as well as some or all of the programmable layers, depending on the complexity and performance requirements of the IP. The programmable metal layers, M3 to M5, are a more mature technology and are used to route the custom applications. Soft, synthesizable, IP will also be routed in these programmable metal layers.
With the capacity and performance optimization inherent in Structured ASIC technology, SoC applications in the millions of gates can operate at speeds up to 200 MHz. Making Structured ASIC technology robust enough to meet the demand of modern SoC applications. That, coupled, with the cost savings afforded by the hybrid nature of the technology, easily demonstrate how Structured ASIC technology can fill the void left by cell-based ASIC and FPGA technologies. Specific data on cost, TTM, performance, capacity, power and quality is provided later in this paper when all three platforms are examined in a side-by-side comparison.
Everyone related to the semiconductor industry, who hasn’t been in a comma for the past three years, has probably noticed the economics changes taking place. Due to the economic recession, companies were particularly sensitive to product cost and TTM requirements. It was during this downward turn in the semiconductor market when the Structured ASIC technology emerged into the market. Do to the cost and TTM benefits of the technology; Structured ASIC products have become highly sought after commodities. In fact, In-Stat/MDR has forecasted that the Structured ASIC market will grow from 0.5% of the total MOS gate array market, last year, to 36.4% by the end of 2007. This equates to a Compound Annual Growth Rate (CAGR) of 144.9%, which is very significant, especially when compared to the 3.2% CAGR of the gate array market. The graph shown in Figure 3 illustrates the growth of the Structured ASIC market through 2007.
AMI Semiconductor was one of the first companies to offer Structured ASIC technology, with its XPressArray product line. Once demand for Structured ASIC technology increased, other companies, scrambled to catch-up. In the last six months more than half-a-dozen companies have announced Structured ASIC product lines. A detailed comparison of Structured ASIC suppliers is provided later in this paper.
Structured ASICs are primarily consumed by markets focused on complex digital designs. These include the Electronic Data Processing (EDP), communication, consumer, industrial, medical, military and automotive markets. The communication market is forecasted to dominate the Structured ASIC market through 2007, consuming over half (52%) of the market in the forecast period. The second largest consumer of Structured ASICs will be the EDP market with the industrial and medical markets coming in at a close third. Figure 4, shown below, illustrates the market consumption of Structured ASIC products through 2007.
2. ANALYSIS OF SOC DESIGN ISSUES
The paper titled ‘FPGA to ASIC Strategy for Communication SoC Designs’ , explores the key issues of SoC design: Cost, TTM, Capacity, Performance, Power, Quality and IP integration. Due to the critical nature of all of these issues, when designing SoC applications, this paper reviews them again in the framework of the Structured ASIC.
Cost is probably the number one issue, especially in light of current market conditions. There are two types of cost associated with a SoC product: development cost (NRE) and manufacturing cost (per-unit). As discussed previously, Structured ASIC products fill the void for mid-volume applications. What is surprising is just how fast Structured ASICs become a cost-effective solution, in terms of volume. Figure 5, shown below, illustrates the market for Structured ASICs in term of volume.
Clearly, if the application calls for more than a few thousand units per year, FPGA high per-unit cost make it a poor choice for a hardware platform. Also, just as clear, the exorbitant NRE cost of cell-based ASIC, make it a poor choice until volumes exceed 250k units per year and possibly not even then, depending on the application. Structured ASIC technology will prove to be the most cost effective solution for most applications requiring a volume between 5k and 250k units per year.
Time-to-Market or TTM is another very important issue that has to be taken into account when starting a new SoC development project. TTM is not only critical in beating competitors to market but it also impacts the overall cost of the project. The longer it takes getting a product to market the greater the impact to market share. If TTM is the biggest factor for a particular application, then no other platform can match the TTM benefits of the FPGA platform. Basically there is zero time from design completion to prototypes. However, if the application is going to have any significant volume, then FPGAs become too expensive. The next best solution, from a TTM perspective is the Structured ASIC. Due to its hybrid nature, a Structured ASIC can go from design completion to prototypes in less than 13 weeks, where a cell-based solution could take six months or longer. It is possible to get the TTM benefits of FPGA technology and still achieve the cost savings of a Structured ASIC as volume increases. To accomplish this one must first prototype and go into limited production using FPGA technology. Then, while production is ramping-up, convert the FPGA design into a Structured ASIC using the FPGA to ASIC translation methodology . Using this methodology the product is ready for the market as soon as the system is completely designed and within 13 weeks of starting limited production runs, the Structured ASIC version of the device will be ready for full production runs. This methodology flow fits well with beta trials that most companies like to do on new products, prior to committing to full production.
Capacity is another key issue when talking about SoC design. Modern day SoC applications can easily reach into the millions of gates. Size may be the determinate factor when considering which hardware platform to utilize. Most current Structured ASIC products can easily support designs up to two million gates. There are a few suppliers that offer Structured ASIC products that support 5 to 10 million gate designs, however, in order to support cell-based type capacities, expensive leading-edge fab technologies must be used, greatly reducing the cost-effectiveness of the product. Most of the next generation Structured ASIC products will be able to support 4+ million gates.
Performance runs along the same line as capacity. Most of the Structured ASIC products currently available on the market support clock speeds up to 200 MHz. Higher performance products are available but only by utilizing expensive leading- edge fab technologies. Too maintain cost-effectiveness, Structured ASIC products must lag state-of-the-art, therefore, real high performance systems will incur cost similar to a cell-based design. However, it is possible to support localized high-performance applications such as gigabit SerDes in current Structured ASIC technology with less expensive process technologies. Hard, embedded, IP blocks with deterministic timing can be used for such applications and since only a very small portion of the design is running at max speed, the performance can be met in older technologies.
Power is another critical resource in modern SoC applications. This is especially true in the communication and consumer markets where electronic devices keep getting smaller and smaller. The available power decreases while at the same time the complexity of the device increases. All this means that SoC designs used in such devices must conserve as much power as possible. Lower power equates to smaller less expensive power supplies, savings on board space and fewer cooling components, which all help to reduce overall cost. Structured ASIC products consume slightly more power than cell-based devices but they also consume order-of-magnitudes less power than FPGAs. Structured ASIC technology makes a good choice for a hardware platform, from a power perspective, for all but the most power stringent systems.
Simply due to their field programmable nature, FPGA technology offers the greatest benefit from a design cycle-time, point-of-view. If an error is encountered in the design while testing the silicon, the designer simply needs to re-program the FPGA to execute the ECO. Cell-based ASIC products have the greatest impact to budget ($300-500k) and schedule (26 weeks), should an ECO be required. Structured ASICs, due to their hybrid nature, can go through an ECO cycle, without breaking the bank or the market window. Since the base is pre-verified, the ECO will only impact the upper metal layers, which are in a mature, often internal, fab technology, allowing a fast re-spin (< 13 weeks) at low cost (~$50k), should one be required.
Design reuse in the form of proven IP cores can greatly reduce TTM and increase quality for SoC designs. According to Dataquest by 2010 the percentage of IP contained in a SoC application is predicted to grow to 95%. There are three types of IP that can be utilized in a SoC design: soft, firm and hard IP. Soft IP is synthesizable and offers the most flexibility. However, timing closure must be met for every application, increasing the risk of utilizing soft IP for high-performance applications. Firm IP is IP that has been synthesized into gates for the target technology. Firm IP provides less risk than soft IP but not as much flexibility. Hard IP is a block of IP that has been completely routed and timing closure on that block has been met. In other words, hard IP blocks have pre-determined timing. Hard or embedded IP blocks must be used for high performance applications. Embedded IP is also used for the most common functions, regardless of performance, functions used in a vast majority of designs. By priority the following functions are usually embedded in Structured ASIC products: IO cells, SRAM, Timing Generators (PLL/DLL), SerDes, MPU and DSP. FPGAs embed a similar set of functions and cell-based ASIC are usually full custom designs with no pre-embedded IP functions at design start. That is not to say that hard IP cannot be utilized in cell-based ASICs, in-fact, just the opposite is true. Any soft, firm or hard piece of IP can be used in a cell-based ASIC design. However, Structured ASICs and FPGAs contain hard embedded IP that has been fully verified and characterized for that architecture, at the system level, prior to the start of the application development. This provides a usable sub-system of IP that the SoC designer does not have to verify or de-bug, saving considerable time during the design cycle.
3. STRUCTURED ASIC SUPPLIERS
Due to the rapid growth of the Structured ASIC market, 144% CAGR by 2007, we have born witness to a number of semiconductor companies who have announced products that fit the generic definition of the Structured ASIC. AMI Semiconductor was one of the first companies to introduce Structured ASIC products to the market but by the end of the year, there will be more than a dozen companies who offer this type of product. Figure 6 list the vendors who currently offer Structured ASIC products.
Throughout this paper three different hardware platforms have been discussed that can be used to implement SoC designs: cell-based ASIC, FPGA, and Structured ASIC. All three have their advantages, depending on business and design requirements. The two most important business requirements are cost and TTM. These requirements are directly related to the forecasted volume of the application and market demand. For SoC applications that are forecasted to only achieve low volumes (less than 5k units per year) then FPGA technology is the best choice for a hardware platform. FPGAs also provide the fastest TTM to market, cementing the fact, that they are the ideal hardware platform for low volume applications. For high volume SoC applications (> 250k units per year) the best choice for a hardware platform is probably a cell-based ASIC. However, cell-based products have the longest design and manufacturing cycles, which negatively impact the products TTM. If the design is very sensitive to TTM requirements, then a Structured ASIC hardware platform may make more sense, even for these high volume applications. For SoC applications ranging from 5k to 250k units per year, the answer is clear. Structured ASIC technology makes the most business sense for all mid-volume applications.
On the technical side the delineating lines are not as clear-cut. Cell-based ASICs provide greater capacity, performance and power conservation than either Structured ASICs or FPGAs. Similarly, Structured ASICs provide greater performance, capacity and power conservation than FPGAs. So one could conclude that cell-based ASIC is the best choice, Structured ASIC is the second best choice and FPGA is the worst choice for a hardware platform from a purely technical perspective.
However, there is another technical characteristic equally important for SoC applications and that is the availability of proven IP. Cell-based ASICs can utilize hard, firm and soft IP. However, even though each individual block of IP may be mature and proven, all of the IP utilized in the application must still be integrated and fully verified at the system level. Structured ASICs and FPGAs provide embedded sub-systems of proven IP, which have been fully verified at the system level and characterized for the specific architecture. This embedded IP sub-system significantly reduces design risk and shortens the design cycle of the product. Also, for most SoC applications, Structured ASICs and FPGAs provide sufficient capacity and performance. FPGAs, however, consume far more power than a Structured ASIC, so unless field programmability is a mandatory system requirement, Structured ASIC technology will make the most sense for all but the highest-end SoC applications.
Given their business advantages and technical capabilities, it is clear, that for mid-volume SoC applications, Structured ASIC technology is the future.
 Dataquest; “ASIC Design Times Spiral Out of Control”; Smith, Gary; 01/02
 In-Stat/MDR; “Structured ASICs: The Preferred Design Solution for the Future”; Worchel, Gerald; 07/03
 AMIS; “FPGA to ASIC Strategy for Communication SoC Designs”; Mosher, Rick; 10/02
 Synopsys; “The Growing Semiconductor Zoo”; Camposano, Raul Dr.; 2003