Hearing-aid SoC: Tiny gear, big challenges

For example, one state-of-the-art design called for a 0.13-micron device combining more than 200,000 gates of digital logic and 100 kbits of memory, as well as a number of analog functions. Yet the device had to operate at under 1 mW. Moreover, the project had to be completed in less than seven months.

Initially, a full-custom approach had been taken in the belief that it would not otherwise be possible to achieve the power target. But it was quickly determined that a standard cell/flow approach could both meet the design's challenging requirements and enable the team to exploit a faster, more efficient design flow.

One way to save significant power is to use a custom cell library and memories, thereby allowing a reduced operating voltage. Further power savings can be realized by careful selection of the available process options and by careful architectural design. To achieve an even more comfortable power dissipation figure, despite what is often an aggressive schedule, experienced designers must tap deep into their knowledge of synthesis, placement, routing and physical analysis tools, as well as their own in-house analog intellectual-property (IP) library, to simultaneously optimize power, size and system performance.

Leveraging the tools

One of the most difficult challenges designers face is verifying at a system level that the behavior implemented at the transistor level matched the specification. Typically, designers would address such a problem by constructing an equivalent Verilog model of the analog subsystem. But that approach carries a high risk of error, particularly since the design contained a large number of macros in some very complex configurations.

Instead, the designer can write Verilog equivalent models of simple primitives and then construct the overall behavioral model of the analog system automatically. For this task, the designer can use the Verilog netlister within the Cadence Virtuoso Schematic Editor, the design composition environment for the Virtuoso custom design platform and the analog schematics. The primitive models are simple enough to be written and verified by the designer of the individual analog block as part of the transistor-level design. That guarantees that each model reflects the silicon implementation.

This approach eliminates most of the risk of a mismatch associated with a conventional strategy of having an independent system-modeling expert write the model. To verify a time-multiplexed general-purpose successive approximation A/D converter, for example, the designer can write primitive models for simple elements such as custom logic gates, the transmission gate switches used to construct the analog multiplexer and the successive-approximation comparator. Then designers can build the overall system model of the A/D subsystem from the netlisting of the primitives and the synthesized controller logic.

This methodology ensures that the Verilog model was consistent with the schematic. Since the model can be built from the connectivity of the master analog schematics, it can be automatically maintained as the design evolves. Because much of the verification of the analog model is handled automatically as part of the Verilog simulations, valuable time can be cut out of the development cycle.

While power savings can be achieved by designing clock gating and sleep modes into the digital portions of the SoC, the sophisticated use of some advanced features in the tools during the synthesis phase of the flow can also play a key role. For instance, by using the low-power synthesis (LPS) capabilities embedded in Cadence Physically Knowledgeable Synthesis (PKS), a tool that takes advantage of physical layout during the synthesis process to achieve timing closure, it's possible to achieve approximately a 5 percent reduction in power consumption.

Typically, engineers run a first pass at synthesis and then perform a gate-level simulation. From that simulation a toggle chain file can be created and the LPS capabilities in PKS invoked. The toggle count format provides an average switching activity for the nets over time. LPS can use this capability to focus on nets with high switching activity and automatically optimize the design over multiple passes.

To accelerate the development cycle and still meet stringent power budgets, the Cadence Encounter digital IC design platform and the Cadence Incisive unified simulator can be used to estimate power consumption during each iteration of the design. Designers ran gate simulations and generated vector change dump files for input into the tool. Since the files can be up to several gigabytes large, a decision may have to be made to select several "windows" where the designers could capture how the device operated in several modes and, in the process, reduce the size of the file and make it more manageable. Next, Spice simulations should be run on a simple logic gate in the target technology, and those results can then be used to calibrate the power values.

IP reuse

Another way to shorten the design cycle is to reuse analog IP. The unusually low-power requirements of the earpiece mean that there are few preexisting blocks that can be used off-the-shelf, but by drawing upon a design team's diverse experience with previous analog designs, existing IP blocks can be tweaked to minimize power consumption.

A designer could take a silicon-proven bandgap reference block from serdes IP originally developed for a 0.13-micron process and, by slightly increasing the layout, cut the power consumption by a factor of 10. Or an oscillator circuit topology developed for a low-power RFID chip could be used to create an ultralow-power sigma-delta audio converter by combining a sigma-delta architecture developed for a PC codec with a low-power op amp topology originally designed for a high-speed A/D.

Mark Forbes (mforbes@cadence.com) is principal design engineer, Dave Johnson (davidjon@cadence.com) is lead design engineer and Graham Inglis (inglis@cadence.com) is senior services manager at the Engineering Services Group of Cadence Design Systems Inc. (San Jose, Calif.).

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