Sonet CMOS transceiver hits 10 Gbits/s

We developed a single-chip full-rate 4:1 serializer/deserializer chip consuming less than 1 watt in a standard 0.13-micron CMOS technology, which was described at the International Solid-State Circuits Conference in February. Previous comparable designs were commonly designed in silicon geranium and BiCMOS technologies.

In addition, we devised a special power supply concept to suppress crosstalk between the receiver (RX) and transmitter (TX) side of the transceiver. This was done along with a novel high-Q notched inductor that is laid out in the voltage-controlled oscillators (VCOs), and whose phase jitter is five times below Sonet specifications.

The XT38702 is a completely integrated transceiver comprising a limiting amplifier, clock and data recovery, demultiplexer and multiplexer (demux and mux) and clock-multiplying unit (CMU). No additional external components are needed to operate the device, which features power consumption of less than 1 W.

Because of the integrated limiting amplifier, the input sensitivity of the 10-Gbit/second serializer/deserializer is less than 15 millivolts. The transceiver locks automatically to all data rates in the range of 9.95 Gbits/s to 10.7 Gbits/s, making it suitable for most 10-Gbit applications.

See related chart The VCO block contains, among other elements, a single-loop horseshoe inductor that is notched, which greatly reduces skin and proximity effects. Source: Xignal Technologies

The TX consists of a clock-multiplying unit and a 4:1 mux, while the RX comprises a limiting amplifier followed by clock and data recovery and a 1:4 demux. No additional external components are required. All high-speed circuitry is realized in differential current-mode logic employing synthetic inductor loads to increase bandwidth. The circuits are powered by per-sub-block linearly regulated supplies, which allow maximum signal swing without exceeding device breakdown voltages.

RX/TX crosstalk is minimized through local capacitive coupling of the regulated supplies to a common ground plane, as well as by providing a very low-impedance path with as many bond wires as possible to external ground. Since the supply regulators provide isolation of the local supplies from the global one, it is ensured that there is only one low-impedance path from every supply node to external ground. Thus, any undamped LC loops prone to peaking are avoided.

All VCOs share a basic building block and operate at 10 GHz. The block consists of a cross-coupled NMOS differential pair providing the necessary negative transconductance, a single-loop horseshoe inductor, a pn-junction varactor and an array of metal-insulator-metal (MIM) capacitors.

Measurements confirmed that inductance increased by 6 percent and in quality factor by 30 percent to a value of 26 at 10 GHz. The pn-varactors are used for continuous tuning during normal operation of the phase-locked loops (PLLs). Their tuning range is 300 MHz. The MIM capacitors are used to initially calibrate the VCO to a reference clock, achieving an accuracy of 1 percent within a range of 1.2 GHz. This produces a wide tuning range and excellent phase noise, which is essential for CMU performance. The differential pair is embedded into a deep N-well to avoid substrate crosstalk.

The transceiver chip was fabricated in TSMC's C130 0.13m CMOS process. Source: Xignal Technologies

The CMU VCO achieves a phase noise of -118 dBc at 1 MHz, drawing 6.5 mA from a 1.2-volt supply. By keeping the PLL loop bandwidth constant, designers obtained an optimum flat jitter-transfer function of the CMU. To accomplish this, designers compensated for the nonlinear VCO gain characteristic by adjusting the charge-pump current inversely proportional to it. The full-rate design allowed them to decrease incoming data jitter, as the 4:1 mux is retiming the output data at a full 10 GHz. When integrating the device to the requirements of Sonet OC-192 specifications, the chip yields a jitter (rms) of 200 femtoseconds.

The recovered 10-Gbit/s data is fed to a 1:4 demux. The transceiver operates from 9.95 Gbits/s to 10.7 Gbits/s with a bit error rate below 10-12.

Heinz Werker is senior principal at Xignal Technologies AG (Munich, Germany). Co-authors include principal engineer Stephan Mechnig and Xignal senior staff engineers Christophe Holuigue, Christian Ebner, Frederic Roger and Gerhard Mitteregger.