The role of Verification IP in Complex core Design
by Saverio Fazzari, Cadence Design Systems, Inc.Columbia, MD USA Abstract:
This paper describes the role of Verification IP (VIP) in the development and successful usage of complex Semiconductor IP (SIP) cores. The discussion will be based around the development of one such complex core a high performance PCI Express Digital Core developed by Cadence. The increasing complexity of such cores has driven the need for more advanced functional verification techniques to minimize development risk.
The use of standards based verification languages, such as SystemC and Sugar/PSL, provides designers access to key analytical functions such as transactions and assertions, which enable the validation of complex functional behavior. It is important to have testing methods for the verification IP to demonstrate the quality and the interoperability with other parts of the verification environment.
The Cadence Unified Verification Methodology (UVM) can handle functional verification of large IC designs with complex IP blocks, and can be used for SIP development. This methodology will be used to show how the VIP blocks are developed and to highlight the benefits to both IP creators and IC developers.
In addition to describing the specific use of VIP in the Cadence Incisive verification platform for the Cadence PCI Express Digital Core, the paper will discuss the trade-offs in using VIP in general and the current status of the industry. Finally, the paper will explain how to maximize the benefits gained through the best use of VIP. INTRODUCTION
The explosive growth in the electronics industry over the last 15 years has been enabled by the rapid progress of semiconductor technology which has kept pace with the ever demanding market requirements. The desire for companies to incorporate new sets of features, meet performance goals, and hit cost points has lead to strong industry demand for improved technology capabilities. An important trend is the rapid evolution of silicon technology as described by Moores law - taking us to 90 nm technology which can support 100 million gates.
This enormous IC capacity provides the opportunity to embed more functionality into products. The new situation is that design teams cannot utilize all the silicon area effectively given the constraints of the design tools and the schedule. There is a design productivity gap that should be addressed.
One element of the solution to the design productivity gap is to re-use key functions in complex IC designs. The use of pre-defined functional blocks or Intellectual Property (IP) in modern electronic design is now a critical factor in the success or failure of projects. While re-using functional blocks is not new, the level of complexity seen in new IP far exceeds that of basic functional circuit building blocks. These modern IC solutions integrate more and more system functionality into single chips. These System on Chip (SoC) designs provide the flexibility needed to meet todays market requirements. The IP blocks are integrated with newly designed circuitry and other functional blocks to create an overall single IC.
The increased complexity of SoC design and the tasks involved in implementation led to an evolution in the utilization of design teams. Originally the design team would be responsible for all phases of the design, from concept to verification and implementation. It is assumed that a person is able to design a set amount of gates. So as the gate count grows, the number of designers also grows. Unfortunately, larger design teams are less efficient due to communications, work flow, and process control requirements. This creates the need to improve design team productivity and efficiency, by leveraging other resources such as using external IP within the design.
Part of the shift we have seen in the design team organization has revolved around the key capabilities of specific design teams associated with the functional blocks within the design with teams focusing on areas of core competency for the company and looking to other sources for standards based IP blocks.
The need to enhance the efficiency of design teams by focusing on specific functions of the design subsequently led to the development of internal core development groups and the search for external sources of IP. IP design groups have expertise in the particular standard and provide full deliverables needed to integrate the IP into the SoC. The complex IP core would be developed and maintained externally, allowing the SoC design team to focus on their core competency instead.WHAT IS VERIFCATION IP?
The use of Semiconductor IP (SIP) is well established within IC design. It is pre-built functionality that can be used to reduce risk on a SoC project. The delivery package includes items required to implement the IP block within the customers design. Soft IP is shipped in a Hardware Description Language (HDL) format such as Verilog or VHDL which can be synthesized to a range of silicon processes and integrated into the design. Hard IP is targeted at a specific process and deliverables includes guidance on placement of the IP within the design. A key concern to IP users is proof of the functional capability of the core. This typically involves presales discussions about references, licensees, silicon proving, and general maturity of the IP.
HDL based testbenches have been the common verification deliverable for SIP for many years. This is due to the familiarity of the IP design team using the HDL and its associated capabilities. Since the IP complexity was not significant, performance and debugability was not an issue with this approach. The existence of a common approach for both implementation and verification (Verilog or VHDL) ensured compatibility and familiarity for the users of IPs and testbenches designed internally and those designed externally.
PCI Express is becoming the de facto high speed serial interface for a wide range of communication and computing applications. Designed to be backwards compatible with existing PCI, PCI Express competes with other high speed IO standards such as RapidIO and HyperTransport.
Because of the popularity of the PCI Express interface, many companies now offer SIP for PCI Express. The cost of development of this core is significant due to its complexity. The configurable nature of the architecture means that the time taken for development of the test environment is significant. General studies suggest that on average 60 to 70 percent of development schedules are taken up with verification.
In a hypothetical IC design case with a schedule of 1,000 man hours, 600 man hours, or 15 weeks, would be allocated to the verification task. Some customers who were HDL-based for verification told us that half of their verification time is spent creating the testing infrastructure. It is clear that when such a project is scaled to a larger design, it becomes very costly to manage the IC design and verification successfully.
Sixty to seventy percent of design failures are due to logic errors according to most studies. This fact coupled with the example above drives a need for a new and more effective verification approach. Key drivers to be considered include: performance and reusability of the verification solution and compliance to the functional standard in question. The verification effort required in using the IP is critical for success, as this is where the customer expects to see significant savings over traditional verification methods.
The EDA community has worked hard to produce new methodologies to address requirements for verification. These include improved simulation performance, debug features, and advanced verification strategies. The biggest area of potential is in advanced verification techniques. These include transaction-level modeling and support, integrated assertion support, and testbench techniques. These approaches enable the IP user to achieve performance and compliance goals.
Transactional-level modeling allows a designer to accelerate verification through raising the level of design abstraction. Improved performance is an immediate benefit since the simulator has less data to track. There are added benefits for debugging and configuration. Tests can be written and tracked at the packet level which is easier to work with. Many EDA tools provide capabilities for transactional-level analysis. One can count the number of actual memory reads versus having to determine what signals make up those transactions.
Assertions are another powerful tool for verification. Assertions have been around for years, and in their simplest sense they enable designers to pass intent forward to users. This information is used to highlight whether the behavior is correct. They can also be used to drive other tools for different types of analysis.
Advanced verification techniques allow the user to increase the quality and level of verification. New testbench languages such as SystemC and others support more sophisticated types of testing, such as advanced random testing methods. Coverage tools enable the users to determine the how much verification is done on different parts of the code providing some feedback on the quality.
Successful usage of these features in verification methodologies is driven by availability of models targeted to these tools. The development of SIP therefore can leverage these techniques for a more efficient verification process. VIP should be developed so as to fully exercise the protocol implemented by standards based IP. One extension of this is the provision of compliance checking VIP from a standards body or technology leader. VIP blocks might also link the real world SIP signals on the model with the equivalent externally generated transactions to allow for more testing. These same models can dump the data into specialized database for debugging. VIP is a valuable tool to be used in the design methodology: helping SIP development teams test their IP and their end consumers successfully implement and verify the SIP within their SoC design. DEVELOPMENT STRATEGY
The development of the new complex SIP cores requires an environment which supports the use of advanced verification techniques. The test plans for the core, which demonstrate real world scenario testing, improve the overall design quality of the semiconductor design. The SoC developers are starting to use these new techniques as part of their own strategy so they expect their suppliers to be as sophisticated.
As the successful development of SoC products depends increasingly on the correct function of standards-based semiconductor IP, it is essential to increase confidence of the SoC development teams doing the integration of SIP cores. One of the first steps in ensuring this is to assess the maturity of the IP. If large numbers of users have successfully used the IP, then it is very likely that the IP is reliable and bug free and confidence can be increased by talking to reference customers including those who have taken the core to production silicon. There is risk associated with using unproven silicon. With new standards such as PCI Express, the race to develop PCI-Express SoC solutions can mean that SIP cores are integrated in new products prior to seeing working silicon
Another approach in assessing and selecting IP is through industry-defined quality metrics. The industry is defining various metrics to help with the IP selection method, such as the Quality IP (QIP) metric from the Virtual Sockets Interface Alliance (VSIA). Companies should invest reasonable time to properly select and audit IP and should take advantage of resources such as the VSIA QIP. The QIP provides structured questions which benefit from the input of experienced IP developers and users, including Cadence. It allows the SoC consumer to compare many different solutions quickly. This allows smaller SIP providers to compete using an industry standard to promote their capabilities. Looking in further detail at how SIP was developed and tested can provide significant value in assessing the quality and value of the SIP.
A traditional verification method for SIP is use of HDL based testbenches as mentioned earlier. These would be designed to test the known functional behavior as per the IP specification. Tests would be also written for the corner case or unusual scenarios that the IP developer was aware of. HDL based testbench methodologies are starting to be pushed to their limit. The cost of developing truly comprehensive testbenches for increasingly complex IP is growing and the method lacks genuine reusability. HDL based testbenches tend to be design specific and are not necessarily fully reusable. SoC designers are looking to their IP suppliers for test material that can be reused in their overall verification method. VHDL and Verilog are designed as description languages which were extended to handle the verification tasks. There are limitations in test types and how well the simulators can perform with necessary changes for complex designs. To enhance overall quality and performance, high level language based Verification IP becomes a natural upgrade to the testing and monitoring strategy of SIP development.
There has been a recent push for the usage of directed random testing. This technique allows the verification team to simulate variations of the IP behavior to reflect real-world conditions. Large companies might have gathered this data already through historical analysis, but now smaller companies can simulate very similar conditions using the random techniques. This testing mechanism, in conjunction with coverage techniques, enables effective analysis and provides higher confidence in the use of SIP cores in complex SoCs.
There are many different approaches for VIP development, both from a language and methodology perspective. The following sections will discuss usage of SystemC and Property Specification Language (PSL) SIP. It is important to first highlight the development and usage strategy of the VIP. The Cadence Unified Verification Methodology (UVM) is an approach that can help the SIP developer as well as the SoC designer.UVM UTILIZATION
This is an approach to SoC verification developed by Cadence to address the requirements of speed and efficiency. The key concept is the creation of Functional Virtual Prototype (FVP) model. This FVP is a representation of the overall system captured at various levels of abstraction. This model also includes the testbench environment as well. It allows a true top-down design flow with reusability enabling effective architecture tradeoffs that are verified with the context of the overall system
The various levels of the FVP represent the degrees of development. One might have a transaction-level representation which has the interface between internal blocks clearly defined. The individual blocks can then be replaced over time as by gates. The goal is that the test environment remains constant throughout the process whether testing a higher level model or the full gate-level implementation.
The test environment consists of stimulus generation and response checking blocks. Inside each of these would be master and slave VIP transactors connected with a testbench that generates the stimulus and utilizes the verification language to do the sophisticated testing capabilities needed. There are also monitor blocks which provide feedback on the behavior compliance of the overall design as well as individual IPs.
This approach is designed to meet the requirements of users. By clearly defining the structure and providing test capabilities, it is very easy to support mixed-level of abstraction in representations of the design to enable system testing throughout the process. If the SIP development strategy and model deliverables are using a similar methodology, then the SoC developer should be able to bring the IP into their environment with very little effort. More information on the UVM can be found here VERIFICATION IP CREATION
There are many choices to make in the development process. Deciding on the language for VIP development is a critical choice. The ideal target is one that will allow for reusable blocks for verification both by the developer and the SoC integrator. This will help increase the value of the SIP that is being offered. There are two types of VIPs which are typically provided: traffic generations and monitors. There may also be a compliance test suite available where the VIP is made available from the IP standards body or the technology sponsor/leader. It is important to ensure that the SIP is tested against this suite as well.SYSTEMC TRANSACTORS
The transactors are used to mimic the various devices that the SIP will interface with. They enable the SIP verification team to create various real-world scenarios in which their models use high level commands such as READ and WRITE to test behavior. These transactors replicate the accurate signal level behavior and are able to handle various levels of implementation. The language choice needs to handle multiple design environments and fit well into different methodologies.
SystemC is a set of class libraries for C++ which enables transaction-level modeling, and test bench extensions. It has been around for a number of years and is well supported by both EDA and consumer companies. Some reasons to use it are:
- The language is very mature with multiple inputs from different vendors.
- The open source nature of the language means the cost of entry is low.
- The feature set is ideal for the advanced verification techniques previously described such as random testing.
- There is a natural linkage to C/C++ software based environments allowing for Hardware/software verification.
The success of high level languages such as SystemC often depends on a balance between the effort to learn new methods and benefits from using them. Hardware engineers will continue to use HDL testbenches for some time due to familiarity. An advantage of SystemC VIP is it can be wrapped in HDL for legacy integration work. The reusability and speed benefits of high level language based verification methods will increase the use of SystemC verification IP. SoC users are starting make use of the power of SystemC through increased familiarity and, training. Then significant productivity benefits will be enjoyed from these new methods.
Cadence has developed VIP with SystemC to demonstrate the process and enable users to leverage the power of the UVM. These models are able to mimic the behavior of the device reflecting master and slave devices of a particular IP. The user is also able to use a common API to program IP particular commands at the transactional level. This API converts IP specific complex signal-level transactions into simple function calls.
The models include are monitors to help ensure that the protocol behavior is correct by checking for any rules violations. In addition, these monitors also have transaction recording built-in to help with debugging.ASSERTIONS AND PSL
A monitor is a very powerful tool to ensure that the IP behavior is correct, checking to make sure that no invalid transactions occur. There are many ways to check for incorrect behavior and protocol behavior can be coded in different languages.
Assertions are powerful statements that are used to convey intent to end users. Assertions provide access to a whole series of other tools for verification. In simulation, assertions allow the user to accelerate finding the location of bugs since the assertions will highlight whenever failures occur instead of having to debug log files. The assertions are used to help with coverage tools which provide feedback on verification quality. Finally, formal verification tools use assertions in static mode to prove the validity of the design.
When choosing a language for development, it is important to consider a number of factors such as stability, capability, and flexibility. PSL is a standard defined by Acellera that is supported by many companies. IBM developed this technology and it has been used successfully on a large number of designs. PSL is designed as an assertion language so its capabilities are significant. There are other ways to perform many of the features in Verilog or VHDL, but there is typically an overhead in coding up the assertion. An example might be that 20 lines of HDL code can be replaced by one line of a PSL assertion. Finally, the style of PSL allows it to complement existing design HDL languages such as Verilog or VHDL. So PSL becomes a natural choice for assertion implementation.
VIP assertion models provide protocol checking and coverage feedback for the particular IP protocol. These monitors can be used in conjunction with specific assertions that are embedded in the design by the SoC integrator to get a better feel for the correctness of behavior of the overall system.
The Incisive verification platform from Cadence provides some unique benefits for PSL users. PSL is natively supported by the Incisive simulation environment. PSL statements are viewed the same way as HDL statements so breakpoints can be set. The PSL can be used either embedded or in a separate file such as a standalone VIP module. Finally Incisive also provides static technology that supports PSL for formal verification.VIP MARKET STATUS
VIP can enable more efficient verification by offering better performance and better debug capabilities to the developer and integrator. There are, however, issues which limit the adoption of VIP which are very similar to the state of SIP roughly five years ago. At that time, IP consumers were very cautious about the quality and availability of required offerings. Choosing to use VIP creates different risks that need to be considered by the SoC development team. If the cause of an SoC failure is traced to a particular VIP or SIP, then the savings realized by purchasing this IP is lost due to the recovery costs required to get the design implemented. A lot of companies choose to do their own IP development to minimize the risk associated with the IP. But even this does not guarantee success as it is likely that a separate, albeit internal, design team would be responsible for the IP.
The desire is to install the confidence in the SoC user that external IP can be used. As more customers successfully used VIP in tapeouts, other customers began feeling more comfortable using it since all the bugs were flushed out already. An interesting phenomena has started to occur. The VIP that is provided or recommended with the SIP is another quality measure. If the a third party VIP has been used or tested against the SIP, this means a different perspective would have been used in the verification flow possibly catching more issues. If the same group is responsible for development and verification of the SIP, the same possibly incorrect interpretation of the specification would be used throughout the process, so an error might exist. It might also be that there is a dominant VIP choice that it must be tested against. So the VIP can be a useful tool.
The quality metrics from VSIA mentioned earlier provide an additional tool to help establish the relative value of the IP. The VSIA offering provides input for both SIP and VIP models. It is currently in an Alpha phase. One must however consider the source of the IP scoring information. If it is the IP vendor, there is a question about the value of self assessment. Other things to consider include the environment that IP is used in.
An important part of IP usage is the ease of use of the IP within the end users EDA environment. If the model is properly optimized, or specific SIP deliverables are not made available for the EDA tools then additional benefits may be gained. The SoC developer may want to have flexibility in targeting different implementation paths during the life cycle of the product. The verification environment should be as reusable as possible. It may be determined that a particular EDA tool suite should replace the existing one. If models are coded in a proprietary language, there will be a cost of conversion.
The critical variable associated with any design is the verification schedule. The verification methodology should support as many of the advanced techniques as possible. VIP is a needed tool to help in getting the most out of the environment for both IP developer as well as the verification team. Design teams are looking to streamline their process wherever possible. There is a push to move to more top design flows with reusable components. Development of VIP is a valuable approach that can serve two purposes: A tool for improving the quality of SIP and a technology used by the SoC integrator for success. VIP STATUS
A critical part of the success of the SoC development is the verification stage. Typical customer feedback is that after evaluating VIP for use in their SoC verification methodology, either its quality or availability was poor so the design team decided to develop it themselves. To change this perception of VIP, it is imperative to involve EDA vendors more closely. The VIP highlights not only the IP but the capabilities of the verification tools. The IP and the tools are converging together. The actual amount of new design on the SoC is shrinking as the SIP blocks are being used, so verification of the overall system is more critical. This makes the value of VIP more critical to the overall success of SoC designs.
Designers are starting to ask IP developers for availability of VIP. Mentor Graphics just announced an agreement with Verisity to make VIP available for their cores. Synopsys has both SIP and VIP available in their offerings. The Cadence program has third parties test their IP both SIP and VIP inside of the Incisive verification platform. The Cadence program is designed to ensure that all IP vendors can test against the same EDA platform providing high quality choices to SoC designers. It is important to enable smaller vendors to be successful so that both SIP designers and consumers have access to the best choice of technologies.PCI EXPRESS EXAMPLE AND USAGE
Cadence SystemC based VIP for PCI Express provides transactors and monitors. There are Master and Slave transactors designed to mimic the components that SoC environment interfaces with. These models allow memory access, error injection and extensive configurability. This solution is designed to link into multiple HDL environments and allow for the driving of the design through a common API. Cadence used this to demonstrate interoperability with the Cadence PCI Express Digital Core at the Intel Developers forum. CONCLUSIONS
VIP meets an increasingly important piece of the IP developers and SoC integrator overall requirements. If VIP is developed to a high level of quality it validates the quality of the semiconductor IP both stand alone and within the final SoC design. . There are a number of approaches to build the desired VIP blocks. The example listed above as SystemC and PSL shows how the models can be built to augment the overall design ecosystem from SIP developer to integration by the SoC design team.
There is no doubt that enhancing verification methodology so as to increase confidence in the coverage, compliance and interoperability of Semiconductor IP will result in growing adoption of third party SIP for successful SoC design. .This paper has proposed benefits of using VIP during both design and integration of SIP. The SoC designers are starting to demand access to VIP to meet their demanding verification schedules. It is important to continue work with various standards organizations to enable the availability of VIP from multiple sources by providing additional tools to grade the quality of the IP and interoperability with other blocks and EDA environments. Appropriate use of VIP will enable SIP designers to reduce the risks associated with the core development and thereby increase its adoption in SoC designs