Want to know what Samsung is thinking about the future of DRAM and NAND Flash memory technology? That all became clear at an informative and entertaining keynote speech at the MemCon conference August 6, 2013, where Bob Brennan, senior vice president of the Memory System Architecture Lab at Samsung Semiconductor, spoke about "New Directions in Memory Architecture."
Brennan first discussed the challenges of DRAM bandwidth and capacity scaling, and suggested that part of the solution for mobile devices is the adoption of 3D architectures with the JEDEC Wide I/O standard (the latest is Wide I/O 2, as described in this blog post). The other part of the solution is a transition to "tiered" memory architectures.
Brennan went on to discuss NAND Flash capacity scaling, endurance, and bandwidth, and predicted that data centers will increasingly switch from hard disk drives to NAND Flash. Finally, he presented STT-MRAM (magnetoresistive random access memory) as a technology with "persistent performance" that gets close to the capabilities of DRAM.
While it received only a brief mention in Brennan's speech, Samsung announced August 6 that it has started to mass produce the industry's first 3D vertical NAND Flash. Aimed at a wide range of consumer and enterprise applications, the 3D V-NAND technology offers 128 Gbit density in a single chip. This development echoes Brennan's statement that it's very difficult to scale NAND Flash capacity using planar technology, and consequently "you have to go 3D in some way or form."
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