FPGA choice has bearing on signal integrity

Signal integrity is a key criterion when selecting FPGAs for high-speed applications. To support a range of applications, today's FPGAs support a variety of single-ended and differential I/O standards, with options to control drive strength, slew rate and on-chip termination. The flexibility offered by FPGAs can make it difficult to manage signal integrity compared with ASICs or ASSPs. Some FPGA vendors have made significant efforts to design packages and chips that provide robust signal integrity.

This article will detail the do's and don'ts that system designers should keep in mind when selecting the right FPGA to ensure sound signal integrity within a given design.

Do

- Anticipate possible signal integrity challenges early in the design cycle. With how many devices will the FPGA interface? What are the interfaces' bus widths and performance? What are the critical high-speed signals? Which power supplies are required? How can the system be designed (including pin assignment, board routing, board stackup, termination, power decoupling and impedance matching) for robust signal integrity?

- Find out the FPGA design methodology. Was mitigating signal integrity a key criterion during the device planning and design phases? What are the device and package features in the FPGA that will reduce signal integrity failures?

- Make sure the vendor has correlated I/O buffer and package Spice or Ibis models. Ask for correlation data that shows that the simulation results with these models match lab experiment data. Such data proves the vendor has done sufficient signal integrity analysis.

- Ask the vendor for in-house signal integrity characterization results. Signal integrity tests include signal eye diagrams, I/O toggle rates, I/O edge rates (rise and fall times), jitter, I/O pin capacitance, simultaneous switching noise and link-level performance. Each test offers important signal integrity information. For example, high pin capacitance affects signal integrity because of reflections.

- Ask the FPGA vendor to provide a demonstration board to perform signal integrity testing. If test results are satisfactory, try to use the demo board Gerber files as a baseline for your board design. Also ask the vendor for termination recommendations, board guidelines, and I/O placement and chip design recommendations.

Shown is 1.0-Gbit/s LVDS IBIS eye-diagram comparison of FPGAs with 'real' pin capacitance and FPGAs with twice that pin capacitance. Source: Altera Corp.

Don't

- Decide on a vendor without doing a thorough analysis of the FPGA design methodology, design features and device characterization data. Signal integrity tools and support offered by the FPGA vendor must be evaluated. Tools and support include I/O models, pin placement and board design guidelines, demonstration boards and sample Gerber files.

- Let the system timing margin cut close to zero. Make sure that the design has sufficient margin to run reliably at the desired frequency under all operating conditions. When performing timing margin analysis, assume worst-case numbers. Signal characteristics vary under varying temperature and voltage conditions. Having sufficient timing margin will ensure the robustness of the system.

- Ignore the I/O programmability features that the FPGA offers. Today's high-density, high-performance FPGAs provide programmable drive strength, slew rate and on-chip termination settings for single-ended and differential I/O standards. Using the right setting for your system helps provide the optimal signal quality and amplitude. The best way to determine the right setting for a specific application is to perform Ibis or Spice simulations.

- Compare signal integrity results of different FPGAs without understanding the test setup. To get a proper comparison of signal integrity performance among multiple FPGAs, take into account differences in test conditions, board setup and test pattern. Minor variations in the setup can have a significant impact on signal integrity.

- Build a board without performing simulations to predict signal integrity in your system with multiple FPGAs. While performing simulations, take into account board trace impedance, trace length, vias, on-board termination and any other board components that will impact signal integrity. This step prevents expensive and time-consuming board respins.

Lalitha Oruganti (LORUGANT@altera.com), member of the I/O technical staff at Altera Corp. (San Jose, Calif.)