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Design productivity can grow by 8X, says Synopsys VP
Dylan McGrath, EE Times (02/28/2006 8:24 PM EST) SAN FRANCISCO — Productivity — the cost in time and resources that it takes to complete a chip — is the dominant issue in IC design today, according to John Chilton, senior vice president and general manager for Synopsys Inc.'s Solutions group. While the design gap between what the market demands and what the IC industry can supply is growing, Chilton told audience of mostly design and verification engineers at last week's Design & Verification Conference (DVCon) in Santa Clara, Calif, the limitation has seemingly shifted from capability to productivity. "The good news is that we're not hearing so much that we won’t be able to get chips to work, or work fast enough, it’s just that we won’t be able to design them within a reasonable time-frame and budget," Chilton said. For a small fraction of chips, Chilton said, the market is so large that it doesn't matter — chip makers will get them out at all costs. But for the vast majority of devices, the productivity issue is a "crisis," Chilton said. Whereas quality-of-results was once the dominant goal for EDA companies, today it is productivity, Chilton said. But the problem is that productivity in IC design is difficult to even measure, much less improve, he said. Synopsys' Services group, he said, has been working for a couple of years on a set of metrics to track the cost of design and determine if the industry is getting more efficient. Design size, performance, process node, libraries and intellectual property (IP) maturity have been determined to be the main factors in design productivity, Chilton said.
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