Design Reuse
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore


Simple designs aren't easy, speaker says


Breaking News

Most Popular (Updated Daily)

Richard Goering, EE Times
(03/28/2006 8:45 PM EST)
 
SAN JOSE, Calif. — The best designs are simple designs, and the key to successful silicon intellectual property (IP) design is keeping code simple, said Synopsys fellow Michael Keating at the International Symposium on the Quality of Electronic Design (ISQED) here Tuesday (March 28). But that's a complicated matter, he said.

"Ultimately, the quality of a design depends on the simplicity of its execution," Keating said. "The art of design is the art of making the complex appear very simple."

Keating outlined two "basic rules of design" that he said are often violated in practice. One is that if it's not tested, it's broken. Another is that if it's not simple, it will never work.

Keating does IP development work at Synopsys, and during the past year he decided to work on some test chips to implement IP, similar to what customers would do. It was an "eye opening experience," he said.

Click here to read more ...





E-mail This Article Printer-Friendly Page



list: -1223447731.86 seconds
detail: 0.000241041183472 seconds
prov: 0.000330924987793 seconds
end_new