Bluespec Sets New Direction for IP Design, Reuse

Family of IP, ESL Capabilities Accelerate Development, Verification

WALTHAM, Mass. -- February 5, 2007 -- Bluespec(TM) Inc. today set a new direction for electronic system level (ESL) design with the availability of AzureIP(TM) Foundation Library, a family of pre-packaged and verified intellectual property (IP) building blocks and design reuse capabilities to accelerate ESL design and verification.

"ESL IP needs to reinvent the current register transfer level paradigm by addressing the fundamental limitations that hinder the use of RTL IP," remarks Shiv Tasker, Bluespec's chief executive officer. "Specifically, it must be composable, self-documenting, resilient, highly parameterizable, polymorphic, wholly contained and transparent."

With this library and its enabling ESL capabilities, Bluespec, developer of the only ESL synthesis for control logic and complex datapaths in chip design, enables "extreme reuse" and establishes a set of requirements to which all future ESL IP should adhere.

Bluespec's AzureIP Foundation Library gives design teams a path to faster time to market, rapid design composition, including customization and reuse, increased quality and decreased verification costs. Built at the transaction level for quick simulation, blocks can be automatically compiled to efficient, detailed RTL code. Blocks can be used at any level of abstraction, from abstract system level modeling to a more detailed ESL implementation.

Using RTL IP requires that the designer write and methodically verify a significant amount of control code for each instance where the IP is used. Because it is composable, AzureIP automatically generates the control logic that is required for the IP to fit within its context. This correct-by-construction instantiation allows designers to use IP effortlessly without burdening verification.

Similarly, it is self-documenting and offers interfaces for its use that allow designers to use it as a black box. AzureIP cannot be used incorrectly. It affords no ambiguity in its interfaces, but allows sufficient resilience so that the IP can mold itself to its design context. Interface methods formally guarantee that the correct interface protocol and connectivity is in place at instantiation.

AzureIP is parameterized on structure, function and type, such as polymorphism. For example, when used at the system level, a block could be used to hold and dispatch video frames; used elsewhere it could be used to handle pixels. AzureIP is wholly contained which means that it does not require metadata and other information saved in proprietary files in order to be used. The source data is adequate to convey the information required for its composition and use.

These IP-category, re-defining capabilities are not built-in to the tools or unique to the IP, but are transparently native to the Bluespec semantic model. While the AzureIP Foundation Library provides a family of design building blocks, designers and IP vendors can augment the library with their own building blocks and benefit from the capabilities listed above.

The Foundation Library includes many categories of modules, data types and functions: module connectivity and interconnects (wiring, busses and protocols); storage (FIFOs and registers); math (fixed point and complex); aggregation (vectors and lists); finite state machine language for sequential, parallel, condition and loop structures; multi-clock domain (clock synchronizers); and utility blocks (e.g. completion buffer).

Pricing and Availability

AzureIP Foundation Library is shipping now and is included as part of Bluespec's software distribution.

For more details, contact George Harper, Bluespec's vice president of marketing, who can be reached at (781) 250-2200 or via email at george.harper@bluespec.com.

About Bluespec

Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolset, the only one focused on control and complex datapaths, allows ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling (781) 250-2200.