Lattice Announces LatticeECP2M FPGA Solution for PCI Express V1.1

LatticeECP2M PCI Express Core Successfully Tested Against PCI Express Version 1.1 Specifications; Solution Enables Single-Chip, Programmable PCI Express Endpoints

HILLSBORO, OR - March 5, 2007 -Lattice Semiconductor (NASDAQ: LSCC) today announced the expansion of its PCI Express Intellectual Property (IP) core family within its ispLeverCORE™ portfolio. Lattice is adding a new PCI Express x4 IP core solution, optimized for the LatticeECP2M™ low-cost FPGA family. Like the previous PCI Express x1 IP core for LatticeECP2M devices, the x4 version implements a single-chip PCI Express endpoint solution with integrated SERDES that is ideal for high-volume, low-cost and limited form-factor applications. The new LatticeECP2M PCI Express x4 IP core and evaluation board both successfully passed testing against the PCI Express version 1.1 specifications at the February 2007 PCI-SIG workshop, ensuring that Lattice’s solution is interoperable with existing PCI Express-supported systems. The IP core will be supported by the IPexpress™ flow within Lattice’s ispLEVER® 6.1 Service Pack 2, or later, design tool suite.

Lattice’s PCI Express x4 solution includes not only the IP core, but also an evaluation board, demonstration software and drivers. Lattice is the only FPGA supplier to offer single-chip PCI Express solutions with on-board SERDES in both low-cost (LatticeECP2M) and high-end (LatticeSCM™) FPGAs. LatticeECP2M and LatticeSCM evaluation boards are both available in the PCI Express mechanical form-factor compatible with standard motherboards. The demo software utilizes the evaluation boards to demonstrate PCI express endpoint operation, including configuration, memory/register access and simple tests. Demo drivers and API also are available for users who wish to extend the demo capabilities.

“Lattice continues to rapidly expand the breadth and depth of our PCI Express solutions,“ said Stan Kopec, corporate vice president of marketing. “Our unique capability to deliver these solutions on either high-performance or low-cost FPGA platforms is opening up many new opportunities for Lattice. The market increasingly appreciates that our ‘More of the Best’ philosophy is driving a unique suite of truly compelling products."

An Innovative Approach for PCI Express Protocol Implementation

As the successor to the pervasive PCI standard, PCI Express inherits a rich legacy of installed software and applications. PCI Express continues to gain momentum and is poised for widespread deployment across a wide range of applications, including PCs, servers, routers, switches, industrial automation, robotics, medical, graphics/image processing and video capture. With this announcement, Lattice is poised to capitalize on the rapid expansion of the PCI Express market with SERDES-based solutions that address a range of system cost needs.

The LatticeECP2M and IP core offer an innovative approach for PCI Express protocol implementation. The LatticeECP2M core implements the transaction, data link and most of the physical layer in soft IP. The remainder of the physical layer – including clock tolerance compensation, 8b/10b encoding and link synchronization – is completely embedded in the low-cost LatticeECP2M Physical Coding Sublayer (PCS), which fully supports 2.5 Gbps operation. As a result, with the LatticeECP2M core, customers benefit from a high-performance and fully integrated PCI Express solution combined with low-cost PCS/SERDES: a compelling value for high-volume applications.

The LatticeECP2M device family offers additional capabilities that enable single-chip PCI Express solutions. On-board Phase Lock Loops (PLLs) support Spread Spectrum Clocking (SSC) for the system-supplied 100 MHz PCI Express clock and enable direct conversion to the 250 MHz reference clock, while the device remains within PCI Express version 1.1 jitter specifications. This eliminates the need for any external PHY, clock conversion or attenuation chips, driving system cost lower. The combination of lower system cost and single-chip capabilities makes the LatticeECP2M device an attractive alternative to the difficulties posed by other PCI Express offerings, such as competitive FPGAs that require external chips to implement clocking, or off-the-shelf ASSP chips that offer no programmability.

Availability

The LatticeECP2M PCI Express x4 solution will be production released later this month. Lattice’s PCI Express IP cores are supported in ispLEVER design tool suite version 6.1, Service Pack 2 or later. The PCI Express cores can be downloaded from the Lattice website at no charge for a time-limited evaluation within the IPexpress flow of the ispLEVER design tool. The LatticeECP2M device evaluation board is available now with a x4 PCI Express connector. Information about PCI Express IP cores, design tools, boards, demos and drivers can be found on the Lattice website at www.latticesemi.com.

About LatticeECP2M FPGAs

LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low-cost SERDES capability for chip-to-chip and small form-factor backplane applications. The LatticeECP2M family maintains all of the compelling features of the 90nm LatticeECP2™ family that are required for high-volume, cost-sensitive applications, while dramatically increasing memory capacity (ranging from 1.2 Mbits to 5.3 Mbits) and DSP resources (ranging from 24 to 168 multipliers). The SERDES integrated into the LatticeECP2M devices has been engineered as a quad-based architecture with 1 to 4 quads, depending on the size of the device. Each quad features 4 SERDES channels (4 complete TX and RX channels), with each channel featuring power consumption as low as 100mW and supporting data rates from 270 Mbps to 3.125 Gbps. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today’s most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).

The LatticeECP2M family includes five devices ranging in density from 20K to 95K Look-Up Tables (LUTS). Samples of the first member of the LatticeECP2M family, the LatticeECP2M-35, in both 484 and 672 ball fpBGA packages are available now. Lattice plans to bring the remaining members of the LatticeECP2M family to the market during the first half of 2007.

About Lattice Semiconductor

Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.

Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit http://www.latticesemi.com