English
Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
Accelerating development and lowering risk
By Gabe Moretti
April 15, 2008 -- edadesignline.com
The central message of this panel was that the industry must grow from being centered on IP blocks to offer and use IP subsystems. Bill Martin, who chaired the panel stated that the intention should be to remove many of the integration issues design teams struggle with in the effort to meet market introduction deadlines. Mr. Martin observed that in too many cases, engineers want to modify third party IP. But doing this results in destroying the value built into the IP. So tinkering not only raises many verification and support problems, but lowers the value of the IP, resulting in significant inefficiency and thus much higher costs.
Peter Hirt, of ST Microelectronics gave an example of a set top box that has 100 Million transistors, targets the 65 nm process node and is scheduled to be fabricated at 55 nm with optical shrink technology. The connectivity subsystems inside the chip have presented a particular challenge involving connecting third party IP blocks with logic developed in-house.
April 15, 2008 -- edadesignline.com
The central message of this panel was that the industry must grow from being centered on IP blocks to offer and use IP subsystems. Bill Martin, who chaired the panel stated that the intention should be to remove many of the integration issues design teams struggle with in the effort to meet market introduction deadlines. Mr. Martin observed that in too many cases, engineers want to modify third party IP. But doing this results in destroying the value built into the IP. So tinkering not only raises many verification and support problems, but lowers the value of the IP, resulting in significant inefficiency and thus much higher costs.
Peter Hirt, of ST Microelectronics gave an example of a set top box that has 100 Million transistors, targets the 65 nm process node and is scheduled to be fabricated at 55 nm with optical shrink technology. The connectivity subsystems inside the chip have presented a particular challenge involving connecting third party IP blocks with logic developed in-house.
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