Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
EVE to Showcase Transaction-Level Modeling Capabilities During DAC
EVE is adding two new transactors to its extensive library of the most common standard protocols, an AXI Master/Slave transactor and a PCIe Gen 2.0 16x transactor. Both can be connected easily to the design, reducing the setup time for the testbench by eliminating the need for hardware speed bridges or synthesizable testbenches. They offer a high-level application programming interface (API) enabling the designer to quickly create application-oriented test sequences.
In an effort to simplify the creation of transactors for custom protocols and to raise the level of abstraction for hardware debugging, EVE also unveiled ZEMI-3, a new transaction modeling methodology to quickly and easily create custom transactors.
Fully backward compatible with SystemVerilog, ZEMI-3 code works in either emulation or in simulation in the same way, without the need for libraries or conversions.
“ZEMI-3 is a key component of our hardware debugging offering,” states Dr. Luc Burgun, EVE’s chief executive officer and president. “It enables designers to put in place a transaction-level monitoring methodology for debugging hardware design, reducing the time spent analyzing waveforms. ZEMI-3 is a significant improvement in the way transactors are written transactors for custom protocols, leading to fast turnaround time and improved productivity for design teams adopting a transaction-based verification approach.”
With ZEMI-3, it is easy to develop bus functional models (BFMs) because of its embedded behavioral compiler. Clocks between emulated designs under test (DUTs) and the testbench are automatically synchronized when needed, and only when needed. It automatically streams data when possible, making sure the data is moved to its destination before it’s needed.
Other solutions synchronize every event between testbench and emulation so that the testbench and emulation run cycle by cycle, defeating the purpose and benefits of transaction-level modeling. Because ZEMI-3 uses a functional programming paradigm, the transaction is the function call, an intuitive and transparent feature for verification engineers because they do not have to consider the channel of communication.
Says Lauro Rizzatti, vice-president of marketing and EVE-USA general manager: “Transaction-level methodology moves design teams away from in-circuit emulation and synthesizable testbenches. It offers a way to validate software in SoC designs faster –– at megahertz instead of kilohertz speed –– while accelerating the hardware debugging process.”
Pricing and Availability
ZEMI-3 is available now. It is priced at $80,000.
AXI and PCIe Gen 2.0 transactors are available now and are priced from $15,000.
For more information, contact Lauro Rizzatti, general manager of EVE USA and vice president of worldwide marketing. He can be reached at (408) 855-3201 or via email at lauro@eve-team.com. More details about ZEMI-3 can be found at the EVE website located at: http://www.eve-team.com.
About EVE
EVE is the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation. EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its United States headquarters are in Santa Clara, Calif. Telephone: (408) 855-3200. Facsimile: (408) 845-9209. Corporate headquarters are in Palaiseau, France. Telephone: (33) 1 64.53.27.30. Fax: (33) 1 64.53.27.40. Email: info@eve-team.com. Website: http://www.eve-team.com.
|
Related News
- Open SystemC Initiative Announces Proposal for Significant Extensions to Transaction-Level Modeling (TLM) Standard
- The Open SystemC Initiative Announces Availability of the SystemC Transaction-level Modeling Standard with Broad Industry Support
- Konica Minolta Accelerates Hardware Debugging with EVE's ZEMI-3 Transaction-Level Modeling Methodology
- Open SystemC Initiative Announces Completion of New Standard Enabling the Real-World Interoperability of Transaction-Level Models
- Novas, Denali Offer First Transaction-Level Verification and Debugging Environment for PCI Express Design Verification
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |