Networking & Storage Leaders Adopt 100/ 40G Ethernet Verification IP from nSys
Newark, CA, February 25, 2010- nSys Design Systems, offering the world’s largest portfolio of Verification IPs, announced their 100/ 40G Ethernet nVS (nSys Verification Suite), which has been successfully deployed by industry leaders across Ethernet applications.
“The industry leaders who were early adopters, were very happy to see how easily they could create corner cases and find bugs in their DUT. The availability of Compliance Test Suites further accelerated the process of finding bugs without deploying too many resources.” says Jitendra Puri, Engineering Director, nSys. “Our deep understanding of the standards as well as verification methodologies like OVM & VMM, ensured that our customers could leverage advanced features like Constrained Random testing & Coverage Driven Verification easily.”
The 100/ 40G Ethernet nVS is compliant to IEEE 802.3az. The nVS provides support for GMII & XGMII interfaces. It also has support for XSBI/10GBase-R/KR, XAUI/XGXS/10GBase-X/KX4, XFBI, TBI/KX, SGMII interfaces. It supports Auto-Negotiation (clause 73 & 37), Rate Adaptation (clause 72) & FEC (clause 74). It also provides Link State Fault generation mechanism and ull/ Half (1G) Duplex Flow Control Support. The nVS also supports frame types: Data, Control Pause & VLAN to frame.
About Ethernet nVS
The Ethernet nVS is a comprehensive Verification IP solution for pre-silicon functional verification of 100/ 40/ 10/ 1G Ethernet interface designs. It consists of Bus Function Model (BFM), Monitor, Assertion-based Checker and Test Suites for Compliance Testing & Functional Coverage. Ethernet nVS is available in native SystemVerilog (OVM/ VMM) & Verilog, with option of Source Code. To learn more, visit www.nsysinc.com/ethernet.htm
About nSys
nSys offers the World’s Largest portfolio of Verification IPs for standard interfaces/ protocols such as PCIe Gen3/ Gen2/ Gen1, PCI-X, PCI, SR-IOV, Ethernet (100/ 40/ 10/ 1G), Interlaken, USB 3.0/2.0, SATA 3.0, SAS, ATAPI, AXI, APB, AHB, DDR3/2… Each nVS consists of BFM, Monitors, Assertion-based Checkers and Test Suites for Compliance Testing & Functional Coverage. All nVS are available in native Verilog & SystemVerilog (OVM/ VMM), with option of Source Code. The nVS family of VIPs is integrated to work with popular languages, like ‘e’, SystemC, OpenVera and VHDL on all commonly used simulators and platforms. nSys also offers Verification Services like Independent Verification Services, SystemVerilog Migration and Verification Consulting. For more information, please visit www.nsysinc.com
|
Related News
- GbE (10/100/1000Base-T) PHY IP Cores with matching 1G Ethernet MAC, PCS and TSN MAC Controller IP Cores for all your high-speed Ethernet Networking applications is available for immediate licensing
- Synopsys Delivers Industry's First Ethernet 800G Verification IP for Next-Generation Networking and Communications Systems
- Digital Blocks extends leadership of UDP/IP networking with 50 & 100 GbE
- Synopsys Delivers Industry's First Ethernet 400G Verification IP for Next-Generation Networking and Communications Systems
- nSys Offers World's Largest Portfolio of Verification IPs for OVM-Based SystemVerilog Environments
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |