Qualcore Successfully validates USB 2.0 PHY in TSMC 90nm Technology
Sunnyvale, Calif. -- October 6, 2010 - QualCore Logic, a leading provider of digital, mixed-signal and analog intellectual property (IP) for system-on-chip (SoC) designs, today announced that it successfully validated USB 2.0 PHY for US based company - the leading providers of high performance non-volatile solid state drives.
The USB PHY is functional as a Hi-Speed USB Host, Device or OTG PHY with UTMI+Level 3 Interface. The IP is proved in TSMC 90nm Technology
About QualCore Logic
QualCore Logic is the recognized leader of silicon-proven Analog, Mixed-signal and Digital intellectual property (IP) for system-on-chip (SoC) designs for the past 15 years. QualCore’s IP portfolio includes high performance PHYs (DDRs, SerDes etc.), ADCs, DACs, PLLs, DLLs, Special IO’s, Power Management Solutions and various Analog and Digital building blocks. With a large team of expert engineers, we provide best-in-class solutions in all the participating technology areas right from specification till GDSII. It operates design and support centers in Sunnyvale (California) and Hyderabad (India) with more than 50 design experts. Corporate headquarters is located at: 1289 Anvilwood Avenue, Sunnyvale, Calif. 94089. Web Site: http://www.qualcorelogic.com/
|
Related News
- USB 4.0, USB 3.2, USB 3.0, USB 2.0 Silicon Proven PHYs in TSMC, UMC & SMIC Foundries available from T2MIP
- Arasan Announces USB 2.0 PHY in Ultra Low Power TSMC 40LP
- Synopsys Offers First Certified TSMC 90-Nanometer USB 2.0 OTG PHY IP
- Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0
- GOWIN Semiconductor USB 2.0 PHY Interface and Device Controller IPs Achieve USB-IF Certification
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |